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PDF KAI-18000 Data sheet ( Hoja de datos )
| Número de pieza | KAI-18000 | |
| Descripción | Image Sensor | |
| Fabricantes | ON Semiconductor | |
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KAI-18000 IMAGE SENSOR
4320 (H) X 4144 (V) INTERLINE CCD IMAGE SENSOR
JUNE 4, 2014
DEVICE PERFORMANCE SPECIFICATION
REVISION 3.0 PS0067
1 page  
KAI-18000 Image Sensor
Summary Specification
KAI-18000 Image Sensor
DESCRIPTION
The KAI-18000 Image Sensor is a high-performance 18-
million pixel sensor designed for 30 frames/sec video
applications. The 8.0 μm square pixels with microlenses
provide high sensitivity and the large full well capacity
results in high dynamic range. The forty outputs and with
binning capabilities allow for 30 frames per second (fps)
progressive scan video images at a pixel rate of 17 Mhz.
The vertical overflow drain structure provides
antiblooming protection and enables electronic
shuttering for precise exposure control. Other features
include low dark current, negligible lag and low smear.
FEATURES
30 frames per second
17 MHz data rate
Progressive scan
APPLICATIONS
Customer restricted
Parameter
Typical Value
Architecture
Interline CCD; Progressive Scan
Total Number of Pixels
4320 (H) x 4224 (V) = approx. 18.2 M
Number of Effective Pixels
4320 (H) x 4144 (V) = approx. 17.9 M
Number of Active Pixels
4320 (H) x 4160 (V) = approx. 18.0 M
Number of Outputs
40
Pixel Size
8.0 μm (H) x 8.0 μm (V)
Imager Size
47.89 mm (diagonal)
Chip Size
37.00 mm (H) x 36.00 mm (V)
Aspect Ratio
Saturation Signal
1:1
50,000 e-
Peak Quantum Efficiency (QE) 55%
Solar Weighted Average QE
400 to 900 nm
Output Sensitivity
Total Sensor Noise (at 17 MHz)
VCCD Capacity
Dark Current at 20 °C
31%
30 μV/e-
<25 e-
60,000 e-
< 0.5 nA/cm2
Dark Current Doubling
Temperature
7 °C
Dynamic Range
60 dB
Charge Transfer Efficiency
> 0.99999
Blooming Suppression
200X
Smear
Image Lag
-85 dB
<10 e-
Maximum Data Rate
20 MHz
All parameters above are specified at T = 20 °C
www.truesenseimaging.com
Revision 3.1 PS0067 Pg 5
5 Page 
VERTICAL TO HORIZONTAL TRANSFER
V1
V2
V1
VH
KAI-18000 Image Sensor
charge transfer
H2 H1
H2
H1
Figure 5: Vertical to Horizontal Transfer Architecture
When the V1 and V2 timing inputs are clocked, charge in every pixel of the VCCD is shifted one row towards the HCCD.
The last row of gates next to the HCCD has a separate clock line, VH. The timing requirements to meet 30 frames/sec
mandate a very short horizontal retrace time which is insufficient to allow a complete VCCD transfer across the entire
pixel array. To allow enough time for VCCD charge transfer the V1 and V2 clocks are operated during HCCD read out.
This extends the V1 and V2 charge transfer times out to the length of one line time. To prevent charge from the VCCD
from transferring into the HCCD during HCCD readout the last gate, VH, is clocked separately. VH is normally held low
to block transfer from the VCCD to the HCCD. When an entire line has been read out of the HCCD and V1 is low and V2
is high, then VH is rapidly clocked from low to high and back low again in less than 1 µs. The short pulse on VH transfers
the next row into the HCCD. H1 must be high and H2 must be low during the VH transfer time from the VCCD to the
HCCD.
www.truesenseimaging.com
Revision 3.1 PS0067 Pg 11
11 Page | ||
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| PDF Descargar | [ Datasheet KAI-18000.PDF ] | |
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