PDF MT8880C Data sheet ( Hoja de datos )

Número de pieza	MT8880C
Descripción	Integrated DTMF Transceiver
Fabricantes	Zarlink Semiconductor
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No Preview Available ! ISO2 - CMOS MT8880C Integrated DTMF Transceiver Data Sheet Features • Complete DTMF transmitter/receiver • Central office quality • Low power consumption • Microprocessor port • Adjustable guard time • Automatic tone burst mode • Call progress mode Applications • Credit card systems • Paging systems • Repeater systems/mobile radio • Interconnect dialers • Personal computers Description The MT8880C is a monolithic DTMF transceiver with call progress filter. It is fabricated in Zarlink Semiconductor’s ISO2-CMOS technology, which September 2005 Ordering Information MT8880CE 20 Pin PDIP Tubes MT8880CS MT8880CN MT8880CP MT8880CP1 MT8880CS1 MT8880CE1 MT8880CN1 MT8880CSR MT8880CPR 20 Pin SOIC 24 Pin SSOP 28 Pin PLCC 28 Pin PLCC* 20 Pin SOIC* 20 Pin PDIP* 24 Pin SSOP* 20 Pin SOIC 28 Pin PLCC Tubes Tubes Tubes Tubes Tubes Tubes Tubes Tape & Reel Tape & Reel MT8880CPR1 28 Pin PLCC* MT8880CSR1 20 Pin SOIC* Tape & Reel Tape & Reel *Pb Free Matte Tin -40°C to +85°C provides low power dissipation and high reliability. The DTMF receiver is based upon the industry standard MT8870 monolithic DTMF receiver; the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. A standard microprocessor bus is provided and is directly compatible with 6800 series microprocessors. TONE ∑ D/A Converters IN+ IN- GS OSC1 OSC2 Tone Burst Gating Cct. + Dial - Tone Filter Oscillator Circuit Bias Circuit Control Logic High Group Filter Low Group Filter Control Logic Row and Column Counters Digital Algorithm and Code Converter Steering Logic Transmit Data Register Status Register Control Register A Control Register B Receive Data Register Data Bus Buffer Interrupt Logic I/O Control VDD VRef VSS ESt St/GT Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001-2005, Zarlink Semiconductor Inc. All Rights Reserved. D0 D1 D2 D3 IRQ/CP Φ2 CS R/W RS0 1 page MT8880C Data Sheet short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is active. The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. VDD VDD St/GT ESt MT8880C C1 Vc R1 tGTA = (R1C1) In (VDD / VTSt) tGTP = (R1C1) In [VDD / (VDD-VTSt)] Figure 5 - Basic Steering Circuit Guard Time Adjustment The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the formula: tREC = tDP+tGTP tID=tDA+tGTA The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independently the guard times for tone present (tGTP) and tone absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. 5 Zarlink Semiconductor Inc. 5 Page MT8880C Data Sheet V22L + V23L + .... V2nL + V22H + V23H + .. V2nH + V2IMD THD (%) = 100 V2L + V2H Equation 2. THD (%) For a Dual Tone ACTIVE INPUT OUTPUT FREQUENCY (Hz) SPECIFIED ACTUAL %ERROR L1 697 699.1 +0.30 L2 770 766.2 -0.49 L3 852 847.4 -0.54 L4 941 948.0 +0.74 H1 1209 1215.9 +0.57 H2 1336 1331.7 -0.32 H3 1477 1471.9 -0.35 H4 1633 1645.0 +0.73 Table 1 - Actual Frequencies Versus Standard Requirements DTMF Clock Circuit The internal clock circuit is completed with the addition of a standard television colour burst crystal. The crystal specification is as follows: Frequency: 3.579545 MHz Frequency Tolerance: ±0.1% Resonance Mode: Parallel Load Capacitance: 18 pF Maximum Series Resistance: 150 ohms Maximum Drive Level: 2 mW e.g. CTS Knights MP036S Toyocom TQC-203-A-9S A number of MT8880C devices can be connected as shown in Figure 12 such that only one crystal is required. Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left unconnected. 11 Zarlink Semiconductor Inc. 11 Page

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