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PDF MCS7820 Data sheet ( Hoja de datos )
| Número de pieza | MCS7820 | |
| Descripción | USB-2.0 to Two Serial Ports | |
| Fabricantes | Moschip | |
| Logotipo |  |
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MCS7820
USB-2.0 to Two Serial Ports
Features
• USB-2.0 Device Controller
• On-Chip USB-2.0 PHY
• On-Chip Voltage Regulators
• Two 16c450/16c550 compatible UARTs
• Supports SIR IrDA Mode on any/all ports
• Supports RS-232, RS-485 and RS-422
Serial Ports
• 5, 6, 7 and 8-bit Serial Data support
• Hardware and Software Flow Control
• Serial Port speeds from 50 bps to 6 Mbps
• Custom BAUD Rates supported through
external clock and/or by programming the
internal PLL
• On-Chip 512-Byte FIFOs for upstream and
downstream data transfers for each Serial
Port
• Supports Remote Wakeup and Power
Management features
• Serial Port Transceiver Shut-Down
support
• Two-Wire I2C Interface for EEPROM
• EEPROM read/write through USB
• iSerial feature support with EEPROM
• One Bi-directional multi-function GPIO
• On-Chip buffers for Serial Port signals to
operate without external Transceivers over
short cable lengths
• Bus-Powered Device
Applications
• Serial Attached Devices
• Modems, Serial Mouse, Generic Serial
Devices
• Serial-Port Server
• Data Acquisition System
• POS Terminal and Industrial PC
Application Note
• AN-7820
Evaluation Board
• MCS7820-EVB
Package
• 48-pin LQFP Package
Driver Support
• Windows
(98SE / ME / 2000 / XP / 2003 Server)
• Linux Kernel 2.6.5 and above
• MAC 10.2 and above
• Windows CE5.0
• Windows Vista
Utility Support
• Windows based EEPROM Tool
• Mass Production Utility
General Description
The MCS7820 is a USB-2.0 to Dual-Serial Port
device. It has been developed to connect a wide
range of standard serial devices to a USB host.
The MCS7820 has a USB Device Controller
connected to two (2) individual UARTs.
Support for the following serial communication
programs is included:
HyperTerminal, PComm, Windows direct
connection, Windows dial-up connection through
modem, Networking over IrDA and Windows direct
connection over IrDA, Minicom.
Ordering Information
Commercial Grade (0 °C to +70 °C)
MCS7820CV
48-LQFP
RoHS
MosChip Semiconductor ♦ 3335 Kifer Rd, Santa Clara, CA 95051 ♦ Tel (408) 737-7141 ♦ Fax (408) 737-7708
1 page  
Pin Name
27 GND
5A
28 REG02_V18
29 Vcc18A_PLL
30 GND18A_PLL
31 VccK
32 Gnd
33 GPIO
34 RESET
35 EE_SCL
36 EE_SDA
37 GND
K
38 EXT_CLOCK
39 Vcc3IO
40 TXD_2
41 DTR_2_N
42 RTS_2_N
43 RXD_2
44 RI_2_N
45 DSR_2_N
46 DCD_2_N
47 CTS_2_N
48 VccK
MCS7820
USB-2.0 to Two Serial Ports
Type
Power
Power
Power
Power
Power
Power
I/O
Input
I/O
I/O
Power
Input
Power
Output
Output
Output
Input
Input
Input
Input
Input
Power
Functional Description
Ground Pin for 5V Input
Power Pin (1.8V OUTPUT)
PLL Power (1.8V)
PLL Ground
Power Pin (1.8V)
Ground.
GPIO_MODE - Bidirectional GPIO bit. The direction (Input or
Output) is controlled by the DCR for Serial Port #1.
Power-On Reset signal (active high).
2-Wire EEPROM Clock. Default = High (1)
2-Wire EEPROM Data in/out. Default = High (1)
Core Ground.
Input Clock from external world. In normal operation mode,
clock can be supplied to serial ports and used for custom
BAUD Rate of user’s choice. In test mode, clock will be the
test clock input from external world.
Power Pin (D3V3).
Serial Port 3 Transmit Data out to transceiver, or IrDA data
out to IR LED.
Serial Port 3 Data Terminal Ready (in serial protocol), active
low.
Serial Port 3 Request To Send (in serial protocol), active low.
Serial Port 3 Serial Receive Data in from transceiver, or IrDA
data in from IrDA detector.
Serial Port 3 Ring Indicator, active low.
Serial Port 3 Data Set Ready (in serial protocol), active low.
Serial Port 3 Data Carrier Detect (in serial protocol), active
low.
Serial Port 3 Clear To Send (in serial protocol), active low.
Power Pin (1.8V)
Rev. 1.2
Page 5
5 Page 
MCS7820
USB-2.0 to Two Serial Ports
FIFO Control Register (FCR):
The FCR controls the UART behavior in various modes.
Register:
Description:
Offset:
Permissions:
Access Condition:
Default Value:
FCR
FIFO Control Register
2
Write
0x00
Bit[7]
Bit[6]
RHR Trigger Level
Bit[5]
Bit[4]
Reserved
Bit[3]
Reserved
Bit[2]
Flush
THR
Bit[1]
Flush
RHR
Bit[0]
Enable
FIFOs
Bit Description
Operation
0
Enable FIFO Mode
Logic 0: Byte Mode
Logic 1: FIFO Mode
Logic 0: No change
Logic 1: Flushes the contents of RHR, This is operative
1 Flush RHR
only in FIFO mode. The RHR is automatically
flushed whenever changing between Byte Mode
and FIFO Mode. The bit will return to zero after
clearing the FIFO.
Logic 0: No change
2
Flush THR
Logic 1: Flushes the content of the THR, in the same
manner as FCR[1] does the RHR
3 Reserved
Reserved
[5:4] Reserved
Reserved
[7:6] RHR Trigger Level
See Table Below
In 550 Mode, the receiver FIFO trigger levels are
defined by FCR[7:6].
The interrupt trigger level and flow control trigger level
where appropriate are defined by L2 in the table.
L1 defines a lower flow control trigger level. The two
trigger levels used together introduce a hysteresis
element into the hardware RTS/CTS flow control.
In Byte Mode (450 Mode) trigger levels are all set to 1.
Rev. 1.2
FCR[7:6]
2’b00
2’b01
2’b10
2’b11
550 Mode (FIFO = 16)
L1 L2
11
14
18
1 14
Page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCS7820.PDF ] | |
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