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PDF BR25H010-W Data sheet ( Hoja de datos )
| Número de pieza | BR25H010-W | |
| Descripción | SPI BUS Serial EEPROMs | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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TECHNICAL NOTE
HIGH GRADE Specification HIGH RELIABILITY series
SPI BUS Serial EEPROMs
Supply voltage 2.5V~5.5V
Operating temperature -40°C ~ +125°C type
☆☆
BR25H010-W, BR25H020-W, BR25H040-W, BR25H080-W, BR25H160-W, BR25H320-W
☆ : Under development
●Description
□□□BR25H
-W series is a serial EEPROM of SPI BUS interface method.
●Features
● High speed clock action up to 5MHz (Max.)
● Wait function by HOLDB terminal.
● Part or whole of memory arrays settable as read only memory area by program.
● 2.5～5.5V single power source action most suitable for battery use.
● Page write mode useful for initial value write at factory shipment.
● Highly reliable connection by Au pad and Au wire.
● For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1)
● Auto erase and auto end function at data rewrite.
● Low current consumption
At write action (5V) : 1.5mA (Typ.)
●Page write
Number of
pages
At read action (5V)
: 1.0mA (Typ.)
At standby action (5V) : 0.1μA (Typ.)
● Address auto increment function at read action
Product
number
● Write mistake prevention function
Write prohibition at power on.
Write prohibition by command code (WRDI).
Write prohibition by WPB pin.
Write prohibition block setting by status registers (BP1, BP0)
Write mistake prevention function at low voltage.
● SOP8, SOP-J8 Package
● Data at shipment Memory array: FFh, status register WPEN, BP1, BP0 : 0
● Data kept for 40 years.
● Data rewrite up to 1,000,000times.
16 Byte
BR25H010-W
BR25H020-W
BR25H040-W
32 Byte
BR25H080-W
BR25H160-W
BR25H320-W
●BR25H series
Capacity
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
32Kbit
Bit format
128×8
256×8
512×8
1K×8
2K×8
4Kx8
Type
BR25H010-W
BR25H020-W
BR25H040-W
BR25H080-W
BR25H160-W
BR25H320-W
Power source
voltage
2.5~5.5V
2.5~5.5V
2.5~5.5V
2.5~5.5V
2.5~5.5V
2.5~5.5V
SOP8
●
●
●
●
●
●
SOP-J8
●
●
●
●
●
●
Ver A. Aug. 2007
1 page  
30
Ta=-40℃
20 Ta=25℃
Ta=125℃
10
SPEC
0
-10
-20
0
1234
Vcc[V]
Fig.21 SI setup time tDIS
5
100
Ta=-40℃
80 Ta=25℃
Ta=125℃
60
SPEC
6
40
20
0
0123456
Vcc[V]
Fig.24 Data output delay time tPD2(CL-30pF)
80
60 Ta=-40℃
Ta=25℃
40 Ta=125℃
SPEC
20
0
-20
0123456
Vcc[V]
Fig.27 HOLDB release hold time tHRH
100
80
Ta=-40℃
Ta=25℃
Ta=125℃
60
40 SPEC
20
0
0123456
Vcc[V]
Fig.30 Output rise time tRO
50
Ta=-40℃
40 Ta=25℃
Ta=125℃
30
SPEC
20
10
0
0123456
Vcc[V]
Fig.22 SI hold time tDIH
120
100 SPEC
80 Ta=-40℃
Ta=25℃
60 Ta=125℃
40
20
0
012345
Vcc[V]
Fig.25 Output disable time tOZ
6
120
100
80 SPEC
60
40 Ta=-40℃
Ta=25℃
20 Ta=125℃
0
0123456
Vcc[V]
Fig.28 Time from HOLDB to output High-Z tHOZ
100
Ta=-40℃
80 Ta=25℃
Ta=125℃
60
40 SPEC
20
0
0123456
Vcc[V]
Fig.31 Output fall time tFO
100
80 SPEC
60
40
Ta=-40℃
20
Ta=25℃
Ta=125℃
0
0123456
Vcc[V]
Fig.23 Data output delay time tPD1(CL=100pF)
80
Ta=-40℃
60 Ta=25℃
Ta=125℃
40
20
SPEC
0
-20
0
80
123456
Vcc[V]
Fig.26 HOLDB setting hold time tHFH
60
40 SPEC
20
Ta=-40℃
Ta=25℃
0 Ta=125℃
-20
0123456
Vcc[V]
Fig.29 Time from HOLDB to output change tHPD
8
Ta=-40℃
Ta=25℃
6 Ta=125℃
SPEC
4 Ta=125℃
Ta=-40℃
Ta=25℃
2
0
0123456
Vcc[V]
Fig.32 Write cycle time tE/W
5/16
5 Page 
●Method to cancel each command
○READ
・Method to cancel : cancel by CSB = “H”
○RDSR
・Method to cancel : cancel by CSB = “H”
○WRITE、PAGE WRITE
a：Ope code, address input area.
Cancellation is available by CSB=”H”
b：Data input area (D7~D1 input area)
Cancellation is available by CSB=”H”
c：Data input area (D0 area)
When CSB is started, write starts.
After CSB rise, cancellation cannot be made by any means.
d：tE/W area.
Cancellation is available by CSB = “H”. However, when
write starts (CSB is started) in the area c, cancellation
cannot be made by any means. And by inputting on
SCK clock, cancellation cannot be made. In page write
mode, there is write enable area at every 8 clocks.
Ope code
8 bit
Address
8 bit/16bit
Data
8 bit
Cancel available in all areas of read mode
Fig.46 READ cancel valid timing
Ope code
Data
8 bit 8 bit
Cancel available in all
areas of read mode
Fig.47 RDSR cancel valid timing
Ope code
8bit
a
Address
8bit/16bit
Data
8bit
b
tE/W
d
c
Fig.48 WRITE cancel valid timing
SCK
SI D7 D6 D5 D4 D3 D2 D1 D0
bc
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore
write it once again.
Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
○WRSR
a：From ope code to 15 rise.
Cancel by CSB =”H”.
b：From 15 clock rise to 16 clock rise (write enable area).
When CSB is started, write starts.
After CSB rise, cancellation cannot be made by any means.
c：After 16 clock rise.
Cancel by CSB=”H”. However, when write starts (CSB is started)
in the area b, cancellation cannot be made by any means.
And, by inputting on SCK clock, cancellation cannot be made.
14 15 16 17
D1 D0
ab
c
Ope code
Data
tE/W
8 bit 8 bit
a
c
b
Fig.49 WRSR cancel valid timing
Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once
again
Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,
therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.
○WREN/WRDI
a：From ope code to 7-th clock rise, cancel by CSB = “H”.
b：Cancellation is not available when CSB is started after 7-th clock.
SCK
789
ab
Ope code
8 bit
a
b
Fig.50 WREN/WRDI cancel valid timing
11/16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet BR25H010-W.PDF ] | |
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