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PDF BR25H128F-2LB Data sheet ( Hoja de datos )
| Número de pieza | BR25H128F-2LB | |
| Descripción | Serial EEPROM Series Industrial EEPROM | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Datasheet
Serial EEPROM Series Industrial EEPROM
125℃ Operation SPI BUS EEPROM
BR25H128F-2LB
General Description
This is the product guarantees long time support in Industrial market.
BR25H128F-2LB is a serial EEPROM of SPI BUS interface method.
Features
Long Time Support a Product for Industrial
Applications.
High speed clock action up to 10MHz (Max.)
Wait function by HOLDB terminal.
Part or whole of memory arrays settable as read only
memory area by program.
2.5V to 5.5V single power source action most
suitable for battery use.
Page write mode useful for initial value write at
factory shipment.
For SPI bus interface (CPOL, CPHA)=(0, 0), (1, 1)
Self-timed programming cycle.
Low Supply Current
At write operation (5V) : 1.2mA (Typ.)
At read operation (5V)
: 1.0mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
Address auto increment function at read operation
Prevention of write mistake
Write prohibition at power on.
Write prohibition by command code (WRDI).
Write prohibition by WPB pin.
Write prohibition block setting by status registers
(BP1, BP0).
Prevention of write mistake at low voltage.
Data at shipment Memory array: FFh, status register
WPEN, BP1, BP0 : 0
More than 100 years data retention.
More than 1 million write cycles.
Package
W(Typ.) x D(Typ.) x H(Max.)
SOP8
5.00mm x 6.20mm x 1.71mm
Application
Industrial Equipment
Page write
Number of pages
Product Number
64 Byte
BR25H128F-2LB
BR25H128F-2LB
Capacity Bit Format
128Kbit
16Kx8
Product Number
BR25H128F-2LB
Supply Voltage
2.5V to 5.5V
Package
SOP8
○Product structure：Silicon monolithic integrated circuit
www.rohm.com
©2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This product has no designed protection against radioactive rays
1/28
TSZ02201-0R1R0G100370-1-2
27.Feb.2014 Rev.002
1 page  
BR25H128F-2LB
Datasheet
Serial Input / Output Timing
CSB
SCK
tCS
tSCKS
tCSS
tSCKWL tSCKWH
tDIS tDIH
tRC tFC
SI
SO High-Z
Figure 2. Input timing
SI is taken into IC inside in sync with data rise edge of SCK. Input address and data from the most significant bit MSB.
tCS
CSB
tCSH tSCKH
SCK
SI
tPD tOH
SO
tRO,tFO tOZ
High-Z
Figure 3. Input / Output timing
SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB.
"H"
CSB
"L"
SCK
tHFS tHFH
SI n+1
SO Dn+1
tHOZ
Dn
tHRS tHRH
High-Z
tDIS
n
tHPD
Dn
n-1
Dn-1
HOLDB
Block diagram
CSB
SCK
SI
HOLDB
WPB
SO
Figure 4. HOLD timing
INSTRUCTION DECODE
CONTROL CLOCK
GENERATION
VOLTAGE
DETECTION
WRITE
INHIBITION
HIGH VOLTAGE
GENERATOR
INSTRUCTION
REGISTER
ADDRESS
REGISTER
14bit
DATA
REGISTER
8bit
STATUS REGISTER
ADDRESS
DECODER
14bit
READ/WRITE
AMP
8bit
128K
EEPROM
Figure 5. Block diagram
www.rohm.com
©2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/28
TSZ02201-0R1R0G100370-1-2
27.Feb.2014 Rev.002
5 Page 
BR25H128F-2LB
Typical Performance Curves‐Continued
Datasheet
50
40
Ta= -40℃
Ta= 25℃
Ta= 125℃
30
20
10
SPEC
SPEC
50
Ta= -40℃
40 Ta= 25℃
Ta= 125℃
30
20
10
SPEC
SPEC
0
0 12 34 56
SUPPLY VOLTAGE : VCC［V］
Figure 23. SI Setup Time tDIS
0
0 12 34 56
SUPPLY VOLTAGE : VCC［V］
Figure 24. SI Hold Time tDIH
100
Ta= -40℃
Ta= 25℃
80 Ta= 125℃
60
40
20
SPEC
SPEC
100
80
Ta= -40℃
Ta= 25℃
Ta= 125℃
60
40
20
SPEC
SPEC
0
0 1 2 34 5 6
SUPPLY VOLTAGE : VCC［V］
Figure 25. Data Output Delay Time tPD1 (CL=100pF)
0
0 1 2 34 5 6
SUPPLY VOLTAGE : VCC［V］
Figure 26. Data Output Delay Time tPD2 (CL=30pF)
www.rohm.com
©2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
11/28
TSZ02201-0R1R0G100370-1-2
27.Feb.2014 Rev.002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BR25H128F-2LB.PDF ] | |
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