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BU9832GUL-W PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BU9832GUL-W
기능 WLCSP EEPROM
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BU9832GUL-W 데이터시트, 핀배열, 회로
Datasheet
Serial EEPROM Standard EEPROM
WLCSP EEPROM
BU9832GUL-W (8Kbit)
General Description
BU9832GUL-W is a serial EEPROM of SPI BUS interface method.
Features
„ High speed clock action up to 5MHz (Max.)
„ Wait function by HOLD terminal.
„ Part or whole of memory arrays settable as read only memory area by program.
„ 1.8 to 5.5V single power source action most suitable for battery use.
„ Page write mode useful for initial value write at factory shipment.
„ For SPI bus interface (CPOL, CPHA) = (0, 0), (1, 1)
„ Auto erase and auto end function at data rewrite.
„ Low current consumption
¾ At write action (5V) : 1.5mA (Typ.)
¾ At read action (5V) : 1.0mA (Typ.)
¾ At standby action (5V) : 0.1µA (Typ.)
„ Address auto increment function at read action
„ Write mistake prevention function
¾ Write prohibition at power on.
¾ Write prohibition by command code (WRDI).
¾ Write prohibition by WP pin.
¾ Write prohibition block setting by status registers (BP1, BP0)
¾ Write mistake prevention function at low voltage.
„ Compact package
¾ W(Typ.) x D(Typ.) x H(Max.)
: 2.09mm x 1.85mm x 0.55mm
„ Data at shipment Memory array: FFh, status register WPEN, BP1, BP0 : 0
„ Data kept for 40 years.
„ Data rewrite up to 1,000,000times.
Page write
Product number
BU9832GUL-W
BU9832GUL-W
Type
BU9832GUL-W
Number of pages
32 Byte
Capacity
8Kbit
Bit format
1K×8
Power source
voltage
1.8V to 5.5V
Package
VCSP50L2
Product structure:Silicon monolithic integrated circuit
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ2211114001
This product is not designed protection against radioactive rays
1/26
TSZ02201-0R2R0G100410-1-2
30.AUG.2012 Rev.001




BU9832GUL-W pdf, 반도체, 판매, 대치품
BU9832GUL-W (8Kbit)
Datasheet
Sync data input / output timing
CS
SCK
tCS
tSCKS
tCSS
SI
SO
tSCKWL tSCKWH
tDIS tDIH
High-Z
tRC tFC
"H"
CS
"L"
SCK
tHFS tHFH
SI n+1
SO Dn+1
tHOZ
Dn
HOLD
tHRS tHRH
High-Z
tDIS
n
tHPD
Dn
n-1
Dn-1
Figure 1. Input timing
SI is taken into IC inside in sync with data rise edge of
SCK. IInput address and data from the most
significant bit MSB.
Figure 3. HOLD timing
CS
SCK
SI
SO
tPD tOH
tCS
tCSH tSCKH
tRO,tFO tOZ
High-Z
Figure 2. Input / Output timing
SO is output in sync with data fall edge of SCK. Data is
output from the most significant bit MSB.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
4/26
TSZ02201-0R2R0G100410-1-2
30.AUG.2012 Rev.001

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BU9832GUL-W 전자부품, 판매, 대치품
BU9832GUL-W (8Kbit)
Typical Performance CurvesContinued
Datasheet
Figure 8. “L” output voltage VOL-lOL (Vcc=2.5V)
Figure 9. “H” output voltage VOH-lOH (Vcc=2.5V)
Figure 10. Input leak current lLl (CS, SCK,
SI, HOLD , WP )
Figure 11. Output leak current lLO (SO)
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
7/26
TSZ02201-0R2R0G100410-1-2
30.AUG.2012 Rev.001

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전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

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부품번호상세설명 및 기능제조사
BU9832GUL-W

WLCSP EEPROM

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