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PDF CY7C131 Data sheet ( Hoja de datos )
| Número de pieza | CY7C131 | |
| Descripción | 1K x 8 Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
1K x 8 Dual-Port Static RAM
Features
■ True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■ 1K x 8 organization
■ 0.65 micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: ICC = 110 mA (maximum)
■ Fully asynchronous operation
■ Automatic power down
■ Master CY7C130/130A/CY7C131/131A easily expands data
bus width to 16 or more bits using slave CY7C140/CY7C141
■ BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY
input on CY7C140/CY7C141
■ INT flag for port-to-port communication
■ Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,
52-pin TQFP
■ Pb-free packages available
Functional Description
The CY7C130/130A/CY7C131/131A/CY7C140[1] and CY7C141
are high speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/130A/ CY7C131/131A can be used as
either a standalone 8-bit dual-port static RAM or as a master
dual-port RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi-
processor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. BUSY signals that the port is trying
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
in a unique location (3FF for the left port and 3FE for the right
port). An automatic power down feature is controlled indepen-
dently on each port by the chip enable (CE) pins.
The CY7C130/130A and CY7C140 are available in 48-pin DIP.
The CY7C131/131A and CY7C141 are available in 52-pin
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free
PQFP.
Logic Block Diagram
R/WL
CEL
OEL
R/WR
CER
OER
I/O7L
I/O0L
BUSYL[2]
A 9L
A 0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
I/O7R
I/O0R
BUSYR
A 9R
A 0R
[3]
INTL
CEL
OEL
R/WL
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
CER
OER
R/WR
Notes
1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.
2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.
CY7C140/CY7C141 (Slave): BUSY is input.
3. Open drain outputs: pull-up resistor required.
INTR[3]
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06002 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 09, 2008
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CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Capacitance[10]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max Unit
15 pF
10 pF
Figure 4. AC Test Loads and Waveforms
R1 893Ω
5V
R1 893Ω
5V
5V
OUTPUT
OUTPUT
BUSY
281Ω
30 pF
R2
347Ω
5 pF
R2
347Ω
OR
INT
INCLUDING
JIGAND
INCLUDING
JIGAND
30
pF
SCOPE (a)
SCOPE (b)
BUSY Output Load
ALL INPUT PULSES
(CY7C130/CY7C131 ONLY)
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
250Ω
1.40V
3.0V
GND
10%
90%
90%
10%
≤ 5 ns
≤5ns
Document #: 38-06002 Rev. *E
Page 5 of 19
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CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Switching Waveforms (continued)
Figure 10. Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
ADDRESS LR,
ADDRESS MATCH
CEL
CER
tPS
BUSYR
tBLC
tBHC
CER Valid First:
ADDRESSL,R
CER
ADDRESS MATCH
CEL
tPS
BUSYL
tBLC
tBHC
Left Address Valid First:
ADDRESSL
Figure 11. Busy Timing Diagram No. 2 (Address Arbitration)
tRC or tWC
ADDRESS MATCH
tPS
ADDRESS MISMATCH
ADDRESSR
BUSYR
tBLA
tBHA
Right Address Valid First:
ADDRESSR
tRC or tWC
ADDRESS MATCH
tPS
ADDRESSL
BUSYL
tBLA
ADDRESS MISMATCH
tBHA
Document #: 38-06002 Rev. *E
Page 11 of 19
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY7C131.PDF ] | |
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