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PDF CY7C1307BV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1307BV18 | |
| Descripción | 18-Mbit Burst of 4 Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1305BV18
CY7C1307BV18
18-Mbit Burst of 4 Pipelined SRAM with
QDR™ Architecture
Features
Functional Description
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 4-Word Burst for reducing the address bus frequency
• Double Data Rate (DDR) interfaces on both Read & Write
Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL Inputs and Outputs
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
Configurations
The CY7C1305BV18/CY7C1307BV18 are 1.8V Synchronous
Pipelined SRAMs equipped with QDR™ architecture. QDR
architecture consists of two separate ports to access the
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has dedicated
Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn-around” the data bus required with common
I/O devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the device’s Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 18-bit words (CY7C1305BV18) and four
36-bit words (CY7C1307BV18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K and
C/C) memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
CY7C1305BV18 – 1M x 18
CY7C1307BV18 – 512K x 36
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05629 Rev. *A
Revised April 3, 2006
1 page  
CY7C1305BV18
CY7C1307BV18
Pin Definitions (continued)
Name
GND/72M
NC/72M
GND/144M
GND/288M
VREF
VDD
VSS
VDDQ
NC
I/O Description
Input
Address expansion for 72M. This should be tied LOW on the CY7C1305BV18
N/A Address expansion for 72M. This can be connected to any voltage level on CY7C1307BV18
Input
Address expansion for 144M. This should be tied LOW on CY7C1305BV18/CY7C1307BV18.
Input
Address expansion for 144M. This should be tied LOW on CY7C1307BV18.
Input- Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Reference Outputs as well as AC measurement points.
Power Supply Power supply inputs to the core of the device.
Ground Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
N/A Not connected to the die. Can be tied to any voltage level.
Introduction
Functional Overview
The CY7C1305BV18/CY7C1307BV18 are synchronous
pipelined Burst SRAMs equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, the device completely elimi-
nates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 18-bit data transfers in the case
of CY7C1305BV18 and four 36-bit data transfers in the case
of CY7C1307BV18, in two clock cycles.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is refer-
enced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the rising edge of output
clocks (C and C, or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of input clocks (K and
K). All synchronous data outputs (Q[x:0]) pass through output
registers controlled by the rising edge of the output clocks (C
and C, or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS[0:x]) inputs pass
through input registers controlled by the rising edge of input
clocks (K and K).
CY7C1305BV18 is described in the following sections. The
same basic descriptions apply to CY7C1307BV18.
Read Operations
The CY7C1305BV18 is organized internally as four arrays of
256K x 18. Accesses are completed in a burst of four
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the positive input
clock (K). The address presented to Address inputs are stored
in the Read address register. Following the next K clock rise
the corresponding lowest order 18-bit word of data is driven
onto the Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data
will be valid 2.5 ns from the rising edge of the output clock (C
and C, or K and K when in single clock mode, 250-MHz
device). In order to maintain the internal logic, each read
access must be allowed to complete. Each Read access
consists of four 18-bit data words and takes two clock cycles
to complete. Therefore, Read accesses to the device can not
be initiated on two consecutive K clock rises. The internal logic
of the device will ignore the second Read request. Read
accesses can be initiated on every other K clock rise. Doing
so will pipeline the data flow such that data is transferred out
of the device on every rising edge of the output clocks (C and
C, or K and K when in single clock mode).
When the read port is deselected, the CY7C1305BV18 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the positive output clock (C). This will allow
for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Data register provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
negative input clock (K) the information presented to D[17:0] is
also stored into the Write Data register provided BWS[1:0] are
both asserted active. This process continues for one more
cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the positive clock (K). Doing so will
pipeline the data flow such that 18-bits of data can be trans-
ferred into the device on every rising edge of the input clocks
(K and K).
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1305BV18.
A write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
Document #: 38-05629 Rev. *A
Page 5 of 20
5 Page 
TAP Controller State Diagram[11]
1 TEST-LOGIC
RESET
0
0 TEST-LOGIC/ 1
IDLE
SELECT
DR-SCAN
0
1
CAPTURE-DR
1
0
SHIFT-DR
0
1
EXIT1-DR
1
0
PAUSE-DR
0
1
0
EXIT2-DR
1
UPDATE-DR
1
0
Note:
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
CY7C1305BV18
CY7C1307BV18
SELECT
IR-SCAN
0
1
CAPTURE-IR
0
SHIFT-IR
1
EXIT1-IR
0
PAUSE-IR
1
0
EXIT2-IR
1
UPDATE-IR
1
0
1
0
1
0
Document #: 38-05629 Rev. *A
Page 11 of 20
11 Page | ||
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