AT49F004T Datasheet PDF - ATMEL Corporation
| Part Number | AT49F004T | |
| Description | 4-Megabit Flash Memory | |
| Manufacturers | ATMEL Corporation | |
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Features
• Single Voltage Operation
– 5V Read
– 5V Programming
• Fast Read Access Time - 55 ns
• Internal Erase/Program Control
• Sector Architecture
– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 4K Words (8K bytes) Parameter Blocks
– One 240K Words (480K bytes) Main Memory Array Block
• Fast Sector Erase Time - 10 seconds
• Byte-by-Byte or Word-By-Word Programming - 10 µs Typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low-Power Dissipation
– 50 mA Active Current
– 300 µA CMOS Standby Current
• Typical 10,000 Write Cycles
Description
The AT49F004(T) and AT49F4096A(T) are 5-volt, 4-megabit Flash Memories orga-
nized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufactured
with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times
to 55 ns with power dissipation of just 275 mW. When deselected, the CMOS standby
current is less than 300 µA.
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49F004/4096A locates the boot block at lowest order
addresses (“bottom boot”); the AT49F004T/4096AT locates it at highest order
addresses (“top boot”).
To allow for simple in-system reprogrammability, the AT49F004(T)/4096A(T) does not
require high input voltages for programming. Reading data out of the device is similar
to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus con-
tention. Reprogramming the AT49F004(T)/4096A(T) is performed by first erasing a
Pin Configurations
(continued)
Pin Name
A0 - A18
CE
OE
WE
RESET
RDY/BUSY
I/O0 - I/O14
I/O15(A-1)
BYTE
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy Output
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
4-Megabit
(512K x 8/
256K x 16)
Flash Memory
AT49F004
AT49F004T
AT49F4096A
AT49F4096AT
Preliminary
Rev. 1167A–09/98
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AT49F004/4096A(T)
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F004(T)/4096A(T) features
DATA polling to indicate the end of a program cycle. During
a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle.
T O G G L E B I T : I n a d d i t i o n t o DATA p o l l i n g t h e
AT49F004(T)/4096A(T) provides another method for deter-
mining the end of a program or erase cycle. During a pro-
gram or erase operation, successive attempts to read data
from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop
toggling and valid data will be read. Examining the toggle
bit may begin at any time during a program cycle.
READY/BUSY: For the AT49F004(T), pin 12 is an open
drain READY/BUSY output pin which provides another
method of detecting the end of a program or erase opera-
tion. RDY/BUSY is actively pulled low during the internal
program and erase cycles and it is released at the comple-
tion of the cycle. The open drain connection allows for OR-
tying of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49F004(T)/4096A(T) in the following ways: (a) VCC
sense: if VCC is below 3.8V (typical), the program function
is inhibited. (b) VCC power on delay: once VCC has reached
the VCC sense level, the device will automatically time out
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
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| Information | Total 16 Pages | |
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