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PDF ML7125-001 Data sheet ( Hoja de datos )

Número de pieza ML7125-001
Descripción Bluetooth Smart LSI supporting Core
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No Preview Available ! ML7125-001 Hoja de datos, Descripción, Manual

ML7125-001/ML7125-002
BluetoothSmart LSI supporting Core Specification v4.1
FEDL7125-04
Issue Date: April. 5, 2016
Overview
ML7125-00X (-001/-002) is a series of Bluetooth® Smart LSI integrating Ultra Low Power RF, Baseband,
microproccessor core and peripherals, which has Bluetooth® LE compliant 2.4GHz band radio
communication capability. ML7125-00X is supporting Bluetooth® core specification v4.1, it is suitable for
applications such as Wrist Watch, Remote Controller or PC peripherals. The differences in ML7125-00X
series are operating mode that is supported by each product.
Features
Bluetooth® SIG Core Spec v4.1 compliant, supporting master and slave role function
Ultra Low Power RF block
Cortex-M0+ microprocessor core integrated
96KB ROM (CODE_ROM) for Program code.
28KB RAM (CODE/DATA_RAM) for user program and data processing
Memory retention function while the chip is in deep sleep mode with partial power shutdown
(8KB/28KB scalable)
Bluetooth® LE single mode compliant Baseband controller
3 Operating modes
BACI (Bluetooth Application Controller Interface) mode : Lapis original application interface to
HOST MCU.*1
HCI (Host Controller Interface) mode : Bluetooth® standard interface between controller
(LL+RF-PHY) and protocol stack.
Application mode : Download user application into embedded SRAM, two type of application
are supported, “Standalone type”, “Add-on type”. *2
Simultaneous connection up to 2 devices. (support all master/slave combinations)*1
UART interface
SPI (Slave mode) interface *1
I2C (Master & Slave) interface
GPIO ports
On chip Regulator Linear regulator (MAIN Regulator) or Switching regulator
Low Power Operating mode
Single power supply
1.6V to 3.6V
Operating Temperature
-20 deg.C to +75deg.C
Current Consumptions
Deep Sleep Mode with external Low Power Clock
0.35A *3, 0.90A *4
Deep Sleep Mode with internal Low Power Clock oscillator circuit)
2.60A(TYP) *3, 3.15A(TYP) *4
Idle Mode
below 2.0mA(TYP) (Memory retention, 26MHz clock enabled)
Active TX
below 6.7mA(TYP) (power supply using Switching regulator)
Active RX
below 6.2mA(TYP) (power supply using Switching regulator)
Package
7row x 10column pad WCSP (0.4mm pad pitch LGA type, 4.69 x 3.12)
Pb Free, RoHS compliant
*1 : Supported by ML7125-001 only
*2 : Supported by ML7125-002 only
*3 : APPLICATION RAM no retention
*4 : APPLICATION RAM retention
Note : Unless otherwise stated, features listed above supported by both
products.(*1*2)
1/33

1 page




ML7125-001 pdf
FEDL7125-04
ML7125-001/ML7125-002
SPICLK : SPI SLAVE Clock
E2 SPICLK
TM4
Input
I
--- TM4 : Test mode definition input
UART pins
Pin Name
Pin Name Status in
No ML7125-001 ML7125-002
reset
B1 UART_TXD
*1 High output
C1 UART_RXD
*1
*1: Same as ML7125-001
input
I/O
O2
B2pd
I2C pins
Active
Level
---
---
UART TXD output
UART RXD input
Function
Pin Name
Pin Name Status in
Active
No ML7125-001 ML7125-002
reset
I/O Level
B2 I2C_SCL
*1
C2 I2C_SDA
*1
*1: Same as ML7125-001
Input
Input
B2
B2
--- I2C_SCL
--- I2C_SDA
GPIO pins
Function
Pin Name
Pin Name Status in
No ML7125-001 ML7125-002
reset
I/O
A3 RF_ACTIVE
GPIO0 Low output B2
B3 WAKEUP
GPIO1
Input
B2
A4 IRQ
GPIO2 High output B2
B4 PS_CONTRO
L
GPIO3
Low output B2
Debugger pins
Active
Level
Function
RF_ACTIVE : Status pin indicates RF access
--- activity.
GPIO0 : GPIO inout
WAKEUP : Control pin from HOST to wakeup
--- ML7125-001
GPIO1 : GPIO inout/
IRQ : Status pin indicates interruption reason taken
--- place in ML7125-001
GPIO2 : GPIO inout
PS_CONTROL : Status pin indicates deep sleep
--- mode status.
GPIO3 : GPIO inout
No Pin Name Pin Name Status in I/O Active
ML7125-001 ML7125-002 reset
Level
Function
B5 SWD
*1
A5 SWCK
*1
*1: Same as ML7125-001
input
input
B2
I
--- SWD data inout
--- SWD clock input
Miscellaneous pins
No Pin Name Pin Name Status in I/O Active
ML7125-001 ML7125-002 reset
Level
Function
5/33

5 Page





ML7125-001 arduino
FEDL7125-04
ML7125-001/ML7125-002
DC characteristics
Item
H level Voltage Input
Symbol
VIH1
Condition
(*1) (*2) (*5) (*6)
Min
VDDIO
X0.7
L level Voltage input
VIL1 (*1) (*2) (*5) (*6)
0
LPCLKIN pin
H level Voltage Input
LPCLKIN pin
L level Voltage input
Input leak current
Tri-state output leak
current
H level Voltage Output
L level Voltage Output
Regulator output voltage
Input pin capacitance
VIH2
(*3)
VIL2 (*3)
IIH1
IIH2
IIL1
IOZH
IOZL
VOH1
VIH = VDDIO (*1) (*5)
VIH = VDDIO (*2)(*6)
VIL = 0 V (*1) (*2) (*5)(*6)
VOH = VDDIO (*4) (*5)
VOL = 0 V (*4) (*5)
IOH = 2mA (*4) (*5)(*6)
VDDIO = VDDBAT = 2.0V to 3.6V
VOH2
IOL = 1mA (*4) (*5)(*6)
VDDIO = VDDBAT = 1.6V to 2.0V
VOL1
VOL2
VMAIN_OUT
VSW_OUT
VLP_OUT
CIN
IOH = 2mA (*4) (*5)(*6)
VDDIO = VDDBAT = 2.0V to 3.6V
IOL = 2mA (*4) (*5)(*6)
VDDIO = VDDBAT = 1.6V to 2.0V
MAINREG_OUT pin
SWREG_OUT pin
LPREG_OUT pin
F=1MHz (*1) (*2) (*4) (*5)
1
0
–1
5
–1
–1
–1
VDDIO
0.75
VDDIO
0.65
0
0
1.25
1.25
0.70
–
(Ta = 20 to +75 deg.C)
Typ Max Unit
– VDDIO V
–
VDDIO
X0.3
V
– VDDIO V
– 0.3 V
– 1 A
– 250 A
– 1 A
– 1 A
– 1 A
– VDDIO V
–
–
-
1.35
1.35
0.90
8
VDDIO
VDDIO
0.25
VDDIO
0.35
1.55
1.55
1.10
–
V
V
V
V
V
V
pF
(*1) IO pins with I symbol in pin definition
(*2) IO pins with IPD symbol in pin definition
(*3) IO pins with ISH symbol in pin definition
(*4) IO pins with O2 symbol in pin definition
(*5) IO pins with B2 symbol in pin definition
(*6) IO pins with B2pd symbol in pin definition
11/33

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