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GM72V66841CLT 데이터시트 PDF




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부품번호 GM72V66841CLT 기능
기능 2M x 8-Bit x 4 Bank SDRAM
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GM72V66841CLT 데이터시트, 핀배열, 회로
LG Semicon Co.,Ltd.
Description
The GM72V66841CT/CLT is a synchronous
dynamic random access memory comprised of
67,108,864 memory cells and logic including
input and output circuits operating synchronously
by referring to the positive edge of the externally
provided Clock.
The GM72V66841CT/CLT provides four
banks of 2,097,152 word by 8 bit to realize high
bandwidth with the Clock frequency up to 125
Mhz.
Features
* PC100,PC66 Compatible
7K(2-2-2), 7J(3-2-2), 10K(PC66)
* 3.3V single Power supply
* LVTTL interface
* Max Clock frequency
100/125 MHz
* 4,096 refresh cycle per 64 ms
* Two kinds of refresh operation
Auto refresh/ Self refresh
* Programmable burst access capability ;
- Sequence:Sequential / Interleave
- Length :1/2/4/8/FP
* Programmable CAS latency : 2/3
* 4 Banks can operate independently or
simultaneously
* Burst read/burst write or burst read/single
write operation capability
* Input and output masking by DQM input
* One Clock of back to back read or write
command interval
* Synchronous Power down and Clock
suspend capability with one Clock latency
for both entry and exit
*JEDEC Standard 54Pin 400mil TSOP II
Package
GM72V66841CT/CLT
2,097,152 WORD x 8 BIT x 4 BANK
SYNCHRONOUS DYNAMIC RAM
Pin Configuration
VCC
DQ0
VCCQ
NC
DQ1
VSSQ
NC
DQ2
VCCQ
NC
DQ3
VSSQ
NC
VCC
NC
/WE
/CAS
/RAS
/CS
BA0/A13
BA1/A12
A10,AP
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
JEDEC STANDARD
400 mil 54 PIN TSOP II
(TOP VIEW)
54 VSS
53 DQ7
52 VSSQ
51 NC
50 DQ6
49 VCCQ
48 NC
47 DQ5
46 VSSQ
45 NC
44 DQ4
43 VCCQ
42 NC
41 VSS
40 NC
39 DQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Pin Name
CLK
CKE
CS
RAS
CAS
WE
A0~A9,A11
A10 / AP
BA0/A13
~BA1/A12
DQ0~DQ7
DQM
VCCQ
VSSQ
VCC
VSS
NC
Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address input
Address input or Auto Precharge
Bank select
Data input / Data output
Data input / output Mask
VCC for DQ
VSS for DQ
Power for internal circuit
Ground for internal circuit
No Connection
1




GM72V66841CLT pdf, 반도체, 판매, 대치품
LG Semicon
Pin Description(Continued)
GM72V66841CT/CLT
Pin Name
DQ0 ~ DQ7
(I/O pins)
VCC and VCCQ
(Power supply pins)
DESCRIPTION
Data is input and output from these pins. These pins are the same as those of a
conventional DRAM.
3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output
buffer.)
VSS and VSSQ
Ground is connected. (VSS is for the internal circuit and VSSQ is for the output
(Power supply pins) buffer.)
NC No Connection pins.
Command Operation
Command Truth Table
The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE
and address pins.
Function
Symbol
CKE
n-1 n
CS
RAS CAS
WE
A12~
A13
A10
A0~
A11
Ignore command
DESL H X H X X X X X X
No Operation
NOP H X L H H H X X X
Burst stop in full page
BST H X L H H L X X X
Column address and
read command
READ H X L H L H V L V
Read with auto-Precharge READ A H X L H L H V H V
Column address and
write command
WRIT H X L H L L V L V
Write with auto-Precharge WRIT A H X L H L L V H V
Row address strobe and
bank active
ACTV H X L
L
HHVVV
Precharge select bank
PRE H X L L H L V L X
Precharge all banks
PALL H X L L H L X H X
Refresh
REF/SELF H V L L L H X X X
Mode register set
MRS H X L L L L V V V
* Notes : H: VIH, L: VIL, X: VIH or VIL, V: Valid address input
4

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GM72V66841CLT 전자부품, 판매, 대치품
LG Semicon
CKE Truth Table
GM72V66841CT/CLT
Current
State
Active
Function
Clock suspend
mode entry
CKE
n -1 n CS RAS CAS WE Address
HL H X X X
X
Any Clock suspend
LL X X X X
X
Clock Suspend
Clock suspend
mode exit
LH X X X X
X
Idle
Auto-refresh
command
(REF)
HH
L
L
L
H
X
Idle
Self-refresh
entry
(SELF) H L
L
L
L
H
X
Idle
Self refresh
Power down
Power down
entry
Self refresh
exit
Power down
Exit
HL L H H H
HL H X X X
(SELFX) L H L
HHH
LH H X X X
LH L H H H
LH H X X X
X
X
X
X
X
X
* Notes : H: VIH, L: VIL, X: VIH or VIL.
Clock suspend mode entry: The synchronous
DRAM enters Clock suspend mode from active
mode by setting CKE to Low. The Clock suspend
mode changes depending on the current status (1
Clock before) as shown below.
ACTIVE Clock suspend: This suspend mode
ignores inputs after the next Clock by internally
maintaining the bank active status.
READ suspend and READ A suspend: The
data being output is held (and continues to be
output).
WRITE suspend and WRIT A suspend: In
this mode, external signals are not accepted.
However, the internal state is held.
Clock suspend: During Clock suspend mode,
keep the CKE to Low.
Clock suspend mode exit : The synchronous
DRAM exits from Clock suspend mode by
setting CKE to High during the Clock suspend
state.
IDLE: In this state, all banks are not selected,
and completed Precharge operation.
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부품번호상세설명 및 기능제조사
GM72V66841CLT

2M x 8-Bit x 4 Bank SDRAM

LG Semicon
LG Semicon

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