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GM72V66841ELT 데이터시트 PDF




Hynix Semiconductor에서 제조한 전자 부품 GM72V66841ELT은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 GM72V66841ELT 기능
기능 2M x 8-Bit x 4 Bank SDRAM
제조업체 Hynix Semiconductor
로고 Hynix Semiconductor 로고


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GM72V66841ELT 데이터시트, 핀배열, 회로
Description
The GM72V66841ET/ELT is a synchronous
dynamic random access memory comprised of
67,108,864 memory cells and logic including
input and output circuits operating synchronously
by referring to the positive edge of the externally
provided Clock.
The GM72V66841ET/ELT provides four banks
of 2,097,152 word by 8 bit to realize high
bandwidth with the Clock frequency up to 143
Mhz.
Features
* PC133/PC100/PC66 Compatible
-7(143MHz)/-75(133MHz)/-8(125MHz)
-7K(PC100,2-2-2)/-7J(PC100,3-2-2)
* 3.3V single Power supply
* LVTTL interface
* Max Clock frequency
143/133/125/100MHz
* 4,096 refresh cycle per 64 ms
* Two kinds of refresh operation
Auto refresh / Self refresh
* Programmable burst access capability ;
- Sequence:Sequential / Interleave
- Length :1/2/4/8/FP
* Programmable CAS latency : 2/3
* 4 Banks can operate independently or
simultaneously
* Burst read/burst write or burst read/single
write operation capability
* Input and output masking by DQM input
* One Clock of back to back read or write
command interval
* Synchronous Power down and Clock
suspend capability with one Clock latency
for both entry and exit
* JEDEC Standard 54Pin 400mil TSOP II
Package
GM72V66841ET/ELT
2,097,152 WORD x 8 BIT x 4 BANK
SYNCHRONOUS DYNAMIC RAM
Pin Configuration
VCC 1
DQ0 2
VCCQ 3
NC 4
DQ1 5
VSSQ 6
NC 7
DQ2 8
VCCQ 9
NC 10
DQ3 11
VSSQ 12
NC 13
VCC 14
NC 15
/WE 16
/CAS 17
/RAS 18
/CS 19
BA0/A13 20
BA1/A12 21
A10,AP 22
A0 23
A1 24
A2 25
A3 26
VCC 27
JEDEC STANDARD
400 mil 54 PIN TSOP II
(TOP VIEW)
54 VSS
53 DQ7
52 VSSQ
51 NC
50 DQ6
49 VCCQ
48 NC
47 DQ5
46 VSSQ
45 NC
44 DQ4
43 VCCQ
42 NC
41 VSS
40 NC
39 DQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Pin Name
CLK
CKE
CS
RAS
CAS
WE
A0~A9,A11
A10 / AP
BA0/A13
~BA1/A12
DQ0~DQ7
DQM
VCCQ
VSSQ
VCC
VSS
NC
Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address input
Address input or Auto Precharge
Bank select
Data input / Data output
Data input / output Mask
VCC for DQ
VSS for DQ
Power for internal circuit
Ground for internal circuit
No Connection
This document is a general product description and is subject to change without notice. Hynix semiconductor does not a-s1s-ume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Apr.01




GM72V66841ELT pdf, 반도체, 판매, 대치품
GM72V66841ET/ELT
DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ= 0 V)
Parameter
-7
Symbol
Max
Operating
current
Standby current in
power down
Standby current in
power down
(input signal stable)
Standby current in
non power down
(CAS Latency=2)
Standby current in
non power down
(input signal stable)
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
85
Active standby current
in power down
ICC3P
Active standby current
in power down
ICC3PS
(input signal stable)
Active standby current
in non power down ICC3N
Active standby current
in non power down ICC3NS
(input signal stable)
Burst ( CL= 2 )
operating
current ( CL= 3 )
ICC4
ICC4
Refresh current
ICC5
150
Self refresh current ICC6
- 75
Max
85
150
-8
Max
80
2
2
0.4
15
12
6
5
30
20
120
150
160
1
0.4
-7K
Max
80
120
-7J
Unit Test conditions Notes
Max
80
mA
Burst length= 1
tRC = min
1, 2, 3
CKE = V IL,
mA tCK = 12 ns
5
CKE=V IL,
mA tCK= infinity
6
6,8
CKE,CS = VIH,
mA tCK = 12ns
4
CKE = V IH,
mA tCK = infinity
4
CKE = V IL,
mA tCK = 12 ns,
DQ = High-Z
1,2,5
CKE = V IL,
mA tCK = infinity
2,6
CKE,CS = VIH,
mA tCK = 12 ns,
1,2,4
DQ = High-Z
CKE = V IH,
mA tCK = infinity
2,9
mA tCK = min
120 mA BL = 4
mA tRC = min
1,2,3
3
mA VIH >=VCC - 0.2 7
VIL <=0.2V
7,8
Rev. 1.1/Apr.01
-4-

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GM72V66841ELT 전자부품, 판매, 대치품
GM72V66841ET/ELT
AC Characteristics (Ta = 0 to 70 , VCC, VCCQ = 3.3 V
(Continued)
0.3 V, VSS, VSSQ = 0 V)
Parameter
Write recovery or data-in
to precharge lead time
Active (a) to Active (b)
command period
Refresh period
Symbol
tRWL
tRRD
tREF
-7
- 75
-8
- 7K
- 7J
Min Max Min Max Min Max Min Max Min Max
7 - 7.5 - 8 - 10 - 10 -
14 - 15 - 16 - 20 - 20 -
- 64 - 64 - 64 - 64 - 64
Unit
ns
ns
ms
Notes
1
1
Notes : 1. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.40V.
If tT is longer than 1ns,transition time compensation should be considered.
2. Access time is measured at 1.40V. Load condition is CL = 50pF without termination.
3. tLZ (min)defines the time at which the outputs achieves the low impedance state.
4. tHZ (max)defines the time at which the outputs achieves the high impedance state.
5. tCES define CKE setup time to CKE rising edge except Power down exit command.
Test Condition
• Input and output-timing reference levels: 1.4V
• Input waveform and output load: See following figures
input 2.4V
0.4 V
I/O
80%
20%
tT tT
CL
OPEN
Rev. 1.1/Apr.01
-7-

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