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부품번호 | 74AHC2G00-Q100 기능 |
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기능 | Dual 2-input NAND gate | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 14 페이지수
74AHC2G00-Q100;
74AHCT2G00-Q100
Dual 2-input NAND gate
Rev. 1 — 21 March 2013
Product data sheet
1. General description
The 74AHC2G00-Q100; 74AHCT2G00-Q100 are high-speed Si-gate CMOS devices.
They provide two 2-input NAND gates.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Symmetrical output impedance
High noise immunity
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Low power dissipation
Balanced propagation delays
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AHC2G00DP-Q100 40 C to +125 C TSSOP8
74AHCT2G00DP-Q100
74AHC2G00DC-Q100 40 C to +125 C VSSOP8
74AHCT2G00DC-Q100
Description
Version
plastic thin shrink small outline package; 8 leads; SOT505-2
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
NXP Semiconductors
74AHC2G00-Q100; 74AHCT2G00-Q100
Dual 2-input NAND gate
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
VI input voltage
IIK
input clamping current
VI < 0.5 V
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
IO output current
0.5 V < VO < VCC + 0.5 V
0.5
0.5
[1] 20
[1] -
-
+7.0
+7.0
-
20
25
V
V
mA
mA
mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = 40 C to +125 C
-
75
65
[2] -
75
-
+150
250
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC
VI
VO
Tamb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
VCC = 3.3 V 0.3 V
VCC = 5.0 V 0.5 V
10. Static characteristics
74AHC2G00-Q100
Min Typ Max
2.0 5.0 5.5
0 - 5.5
0 - VCC
40 +25 +125
- - 100
- - 20
74AHCT2G00-Q100
Min Typ Max
4.5 5.0 5.5
0 - 5.5
0 - VCC
40 +25 +125
---
- - 20
Unit
V
V
V
C
ns/V
ns/V
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
74AHC2G00-Q100
VIH HIGH-level
input voltage
VIL LOW-level
input voltage
VCC = 2.0 V
VCC = 3.0 V
VCC = 5.5 V
VCC = 2.0 V
VCC = 3.0 V
VCC = 5.5 V
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min
Max
1.5 - - 1.5 - 1.5
2.1 - - 2.1 - 2.1
3.85 -
- 3.85
-
3.85
- - 0.5 -
0.5
-
- - 0.9 -
0.9
-
- - 1.65 - 1.65 -
-V
-V
-V
0.5 V
0.9 V
1.65 V
74AHC_AHCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2013
© NXP B.V. 2013. All rights reserved.
4 of 14
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12. Waveforms
74AHC2G00-Q100; 74AHCT2G00-Q100
Dual 2-input NAND gate
VI
nA, nB input
GND
VOH
nY output
VOL
VM
t PHL
VM
t PLH
001aae972
Fig 5.
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
The input (nA and nB) to output (nY) propagation delays.
Table 9. Measurement points
Type
Input
74AHC2G00-Q100
74AHCT2G00-Q100
VM
0.5VCC
1.5 V
Output
VM
0.5VCC
0.5VCC
74AHC_AHCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2013
© NXP B.V. 2013. All rights reserved.
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74AHC2G00-Q100 | Dual 2-input NAND gate | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |