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PDF MC100H660 Data sheet ( Hoja de datos )
| Número de pieza | MC100H660 | |
| Descripción | 4-Bit ECL/TTL Load Reducing DRAM Driver | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC100H660 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit ECL/TTL Load Reducing
DRAM Driver
The MC10H/100H660 is a 4–bit ECL input, translating DRAM address
driver, ideally suited for driving TTL compatible DRAM inputs from an ECL
system. It is designed for use in high capacity, highly interleaved DRAM
memory boards, that directly interface to a high speed, pipelined ECL bus
interface, where new operations may be initiated to the board at up to a 50
MHz rate.
The latch provides the capability for the memory controller to propagate
new addresses to different banks without having to wait for the address timing
constraints to be satisfied from a previous memory operation. The dual output
fanout reduces input loading from the controller by a factor of two, thus
significantly improving board etch propagation delays from the controller,
without the need for additional ECL buffering.
The H660 features special TTL outputs which do not have an IOS limiting
resistor, therefore allowing rapid charging of the load capacitance. Output
voltage levels are designed specifically for driving DRAM inputs. The output
stages feature separate power and ground pins to isolate output switching
noise from internal circuitry, and also to improve simultaneous switching
performance.
The 10H version is compatible with MECL 10H ECL logic levels. The
100H version is compatible with 100K levels.
• High Capacitive Drive Outputs to Drive DRAM Address Inputs
• Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise
• Dual Supply
• 10.7 ns Max. D to Q into 300 pF
PIN NAMES
PIN
OGND[0:3]
OVT01, OVT23
IGND01, IGND23
IVT01, IVT23
VEE
VCCE
D[0:3]
Q[0:3]A, Q[0:3]B
LEN
R
FUNCTION
Output Ground (0V)
Output VCCT (+5.0 V)
Internal TTL Ground (OV)
Internal TTL VCCT (+5.0 V)
ECL Neg. Supply (–5.2/ –4.5 V)
ECL Ground (0V)
Data Inputs (ECL)
Data Outputs (TTL levels)
Latch Enable (ECL)
Reset (ECL)
25 24 23 22 21 20 19
Q1B 26
18 IVT23
OGND1 27
17 IGND23
Q1A
OVT01
Q0B
28 16
Pinout: 28–Lead PLCC
1
(Top View)
15
2 14
VCCE
VCCE
D3
OGND0 3
13 D2
Q0A 4
12 R
5 6 7 8 9 10 11
MC10H660
MC100H660
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
LOGIC SYMBOL
ECL Inputs
VEE
DRAM Driver
Outputs
VCCE
Q0A
D0
IVT01
IGND01
DQ
ENR
OGND0
Q0B
OVT01
Q1A
D1 D Q
ENR
OGND1
Q1B
D2
IVT23
IGND23
D3
LEN
R
DQ
EN R
DQ
EN R
Q2A
OGND2
Q2B
OVT23
Q3A
OGND3
Q3B
TRUTH TABLE
D LEN
LH
HH
XL
XX
RQ
LL
LH
L Q0
HL
3/93
© Motorola, Inc. 1996
2–121
REV 5
1 page  
MC10H660 MC100H660
OUTPUT WAVEFORMS
simulated
Example 1. An output load consisting of just CL = 50 pF results in
overshoot at the output Q:
8
6
Q
4
2
0
D
–2
0 25 50 75
TIME
Example 2. In a memory system application, use of an external
source resistor is suggested. Simulations run with RS = 8Ω and
CL = 300pF leads to clean waveforms both at the output, Q, and
at point Qp:
Q
H660 OUTPUT
RS = 8 Ω
QP
CL = 300pF
8
6
4
Q
2
QP
0
D
–2
0 25 50 75
TIME
MECL Data
DL122 — Rev 6
2–125
MOTOROLA
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC100H660.PDF ] | |
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