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PDF MC100H680 Data sheet ( Hoja de datos )
| Número de pieza | MC100H680 | |
| Descripción | 4-Bit Differential ECL Bus/TTL Bus Transceiver | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC100H680 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Differential ECL
Busā/āTTL Bus Transceiver
MC10H680
MC100H680
The MC10H/100H680 is a dual supply 4–bit differential ECL bus to TTL
bus transceiver. It is designed to allow the system designer to no longer be
limited in bus speed associated with standard TTL busses. Using a
differential ECL Bus will increase the frequency of operation and increase
noise immunity.
Both the TTL and the ECL ports are capable of driving a bus. The ECL
outputs have the ability to drive 25 Ω, allowing both ends of the bus line to be
terminated in the characteristic impedance of 50 Ω. The TTL outputs are
specified to source 15 mA and sink 48 mA, allowing the ability to drive highly
capacitive loads.
The ECL output levels are VOH approximately equal to –1.0 V and VOL
cutoff equal to –2.0 V (VTT). When the ECL ports are disabled both EIOx and
EIOxB go to the VOL cutoff level. The ECL input receivers have special
circuitry which detects this disabled condition, prevents oscillation, and
forces the TTL output to the low state. The noise margin in this disabled state
is greater than 600 mV. Multiple ECL VCCO pins are utilized to minimize
switching noise.
The TTL ports have standard levels. The TTL input receivers have PNP
input devices to significantly reduce loading. Multiple TTL power and ground
pins are utilized to minimize switching noise.
The control pins (EDIR and ECEB) of the 10H version is compatible with
MECL 10H ECL logic levels. The control pins of the 100H version are
compatible with 100K levels.
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
• Differential ECL Bus (25 Ω) I/O Ports
• High Drive TTL Bus I/O Ports
• Extra TTL and ECL Power/Ground Pins to Minimize
Switching Noise
• Dual Supply
• Direction and Chip Enable Control Pins
Pinout: 28–Lead PLCC (Top View)
25 24 23 22 21 20 19
T101 26
18 EIO3B
GT2 27
VT1 28
17 VCCO4
16 EIO3
GT1 1
TIO0 2
15 VCCE
14 EIO2B
TDIR 3
13 VCCO3
EDIR 4
12 EIO2
5 6 7 8 9 10 11
PIN DESCRIPTIONS
Pin Symbol
1 GT1
2 TIO0
3 TDIR
4 EDIR
5 EIO0
6 VCCO1
7 EIO0B
8 VEE
9 EIO1
10 VCCO2
11 EIO1B
12 EIO2
13 VCCO3
14 EIO2B
15 VCCE
16 EIO3
17 VCCO4
18 EIO3B
19 ECEB
20 TCEB
21 TIO3
22 GT4
23 VT2
24 GT3
25 TIO2
26 TIO1
27 GT2
28 VT1
Function
TTL Ground 1
TTL I/O Bit 0
TTL Direction Control
ECL Direction Control
ECL I/O Bit 0
ECL VCC 1 (0V) – Outputs
ECL I/O Bit 0 Bar
ECL Supply (–5.2/–4.5V)
ECL I/O Bit 1
ECL VCC 2 (0V) – Outputs
ECL I/O Bit 1 Bar
ECL I/O Bit 2
ECL VCC 3 (0V) – Outputs
ECL I/O Bit 2 Bar
ECL VCC (0V)
ECL I/O Bit 3
ECL VCC 4 (0V) – Outputs
ECL I/O Bit 3 Bar
ECL Chip Enable Bar Control
TTL Chip Enable Bar Control
TTL I/O Bit 3
TTL Ground 4
TTL Supply 2 (5V)
TTL Ground 3
TTL I/O Bit 2
TTL I/O Bit 1
TTL Ground 2
TTL Supply 1 (5V)
9/96
© Motorola, Inc. 1996
2–144
REV 6
1 page  
MC10H680 MC100H680
CONTROL INPUTS
TDIR
EDIR
TCE
ECE
TTL I/O
GND1
TIO0
BLOCK DIAGRAM
EOE
TOE
VCCT1
GND2
TIO1
VCCE
VEE
VCCO1
EIO0
EIO0
ECL I/O
VCCO2
EIO1
EIO1
GND3
TIO2
VCCT2
GND4
TIO3
VCCO3
EIO2
EIO2
VCCO4
EIO3
EIO3
MOTOROLA
2–148
MECL Data
DL122 — Rev 6
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC100H680.PDF ] | |
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