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PDF MC100LVEL51 Data sheet ( Hoja de datos )
| Número de pieza | MC100LVEL51 | |
| Descripción | Differential Clock D Flip-Flop | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Differential Clock D FlipĆFlop
The MC100LVEL51 is a differential clock D flip-flop with reset. The
device is functionally equivalent to the EL51 device, but operates from a
low voltage supply. With propagation delays and output transition times
essentially equal to the EL51, the LVEL51 is ideally suited for those
applications which require the ultimate in AC performance at 3.3V VCC.
The reset input is an asynchronous, level triggered signal. Data enters
the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock. The differential clock inputs of the LVEL51 allow the device to
be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability under
open input conditions. When left open, the CLK input will be pulled down
to VEE and the CLK input will be biased at VCC/2.
• 475ps Propagation Delay
• 2.8GHz Toggle Frequency
• Operates from –3.3V (or 3.3V) Supply
• 75kΩ Internal Input Pulldown Resistors
• >2000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
R1
D2
CLK 3
CLK 4
R
D
Flip-Flop
8 VCC
7Q
6Q
5 VEE
MC100LVEL51
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
TRUTH TABLE
D R CLK Q
LL Z
L
HL Z
H
XH X
L
Z = LOW to HIGH Transition
8/96
© Motorola, Inc. 1996
4–1
REV 1
1 page | ||
| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet MC100LVEL51.PDF ] | |
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