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AD5348 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD5348은 전자 산업 및 응용 분야에서
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부품번호 AD5348 기능
기능 Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs
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AD5348 데이터시트, 핀배열, 회로
Data Sheet
2.5 V to 5.5 V, Parallel Interface
Octal Voltage Output 8-/10-/12-Bit DACs
AD5346/AD5347/AD5348
FEATURES
GENERAL DESCRIPTION
AD5346: octal 8-bit DAC
The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit
AD5347: octal 10-bit DAC
DACs, operating from a 2.5 V to 5.5 V supply. These devices
AD5348: octal 12-bit DAC
incorporate an on-chip output buffer that can drive the output
Low power operation: 1.4 mA (max) at 3.6 V
to both supply rails, and also allow a choice of buffered or
Power-down to 120 nA at 3 V, 400 nA at 5 V
unbuffered reference input.
Guaranteed monotonic by design over all codes
Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
The AD5346/AD5347/AD5348 have a parallel interface. CS
selects the device and data is loaded into the input registers on
the rising edge of WR. A readback feature allows the internal
DAC registers to be read back through the digital port.
Readback
The GAIN pin on these devices allows the output range to be
Buffered/unbuffered reference inputs
set at 0 V to VREF or 0 V to 2 × VREF.
20 ns WR time
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging
Temperature range: –40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
All three parts are pin compatible, which allows users to select
the amount of resolution appropriate for their application
without redesigning their circuit board.
Industrial process control
FUNCTIONAL BLOCK DIAGRAM
VDD AGND DGND
VREFAB
VREFCD
BUF
GAIN
DB1... 1
DB0
CS
RD
WR
A2
A1
A0
CLR
LDAC
INTER-
FACE
LOGIC
AD5348
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC A
STRING
DAC B
STRING
DAC C
STRING
DAC D
STRING
DAC E
STRING
DAC F
STRING
DAC G
STRING
DAC H
POWER-ON
RESET
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
VOUTF
VOUTG
VOUTH
POWER-DOWN
LOGIC
1 Protected by U.S. Patent No. 5,969,657.
VREFGH
Figure 1.
VREFEF
PD
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD5348 pdf, 반도체, 판매, 대치품
AD5346/AD5347/AD5348
Data Sheet
Parameter2
LOGIC INPUTS6
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
LOGIC OUTPUTS6
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
B Version1
Min Typ
Max Unit
1.7
5
±1 µA
0.8 V
0.7 V
0.6 V
V
pF
VDD – 1
VDD
0.5
2.5
1
0.8
0.4
0.12
0.4 V
V
0.4 V
V
5.5 V
1.65 mA
1.4 mA
1 µA
1 µA
Test Conditions/Comments
VDD = 5 V ±10%
VDD = 3 V ±10%
VDD = 2.5 V
VDD = 2.5 V to 5.5 V
ISINK = 200 µA
ISOURCE = 200 µA
ISINK = 200 µA
ISOURCE = 200 µA
VIH = VDD, VIL = GND
All DACs in unbuffered mode. In buffered mode,
extra current is typically x µA per DAC,
where x = 5 µA + VREF/RDAC
VIH = VDD, VIL = GND
1 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.
2 See the Terminology section.
3 Linearity is tested using a reduced code range: AD5346 (Code 8 to Code 255); AD5347 (Code 28 to Code 1023); AD5348 (Code 115 to Code 4095).
4 DC specifications tested with outputs unloaded.
5 This corresponds to x codes. x = deadband voltage/LSB size.
6 Guaranteed by design and characterization, not production tested.
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and the offset
plus gain error must be positive.
Rev. A | Page 4 of 24

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AD5348 전자부품, 판매, 대치품
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input Voltage to GND
VOUT to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
38-Lead TSSOP Package
Power Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
40-Lead LFCSP Package
Power Dissipation
θJA Thermal Impedance (3-layer
board)
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature
Rating
–0.3 V to +7 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–40°C to +105°C
–65°C to +150°C
150°C
(TJ max − TA)/ θJA mW
98.3°C/W
8.9°C/W
(TJ max − TA)/ θJA mW
29.6°C/W
300°C
220°C
AD5346/AD5347/AD5348
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those listed in the operational
sections of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 7 of 24

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