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부품번호 | NB3L204K 기능 |
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기능 | Differential 1:4 HCSL Fanout Buffer | ||
제조업체 | ON Semiconductor | ||
로고 | |||
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NB3L204K
2.5V, 3.3V Differential 1:4
HCSL Fanout Buffer
Description
The NB3L204K is a differential 1:4 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs. Inputs can
directly accept differential LVPECL, LVDS, and HCSL signals.
Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are
accepted with a proper external Vth reference supply per Figures 4
and 6. The input signal will be translated to HCSL and provides four
identical copies operating up to 350 MHz.
The NB3L204K is optimized for ultra−low phase noise, propagation
delay variation and low output–to–output skew, and is DB400H
compliant. As such, system designers can take advantage of the
NB3L204K’s performance to distribute low skew clocks across the
backplane or the motherboard making it ideal for Clock and Data
distribution applications such as PCI Express, FBDIMM, Networking,
Mobile Computing, Gigabit Ethernet, etc.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 14) to GND per Figure 11. Outputs can also interface to
LVDS receivers when terminated per Figure 12.
Features
• Maximum Input Clock Frequency > 350 MHz
• 2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
• 4 HCSL Outputs
• DB400H Compliant
• Individual OE Control Pin for Each Output
• 100 ps Max Output−to−Output Skew Performance
• 1 ns Typical Propagation Delay
• 500 ps Typical Rise and Fall Times
• 80 fs Maximum Additive RMS Phase Jitter
• −40°C to +85°C Ambient Operating Temperature
• QFN 24−pin Package, 4 mm x 4 mm
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• PCI Express
• FBDIMM
• Mobile Computing
• Networking
• Gigabit Ethernet
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MARKING
DIAGRAM
QFN24
4x4
CASE 485DJ
1
NB3L
204K
ALYWG
G
NB3L204K = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information page 13 of this
data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 0
1
Publication Order Number:
NB3L204K/D
NB3L204K
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
RPD − Pull−down Resistor
Moisture Sensitivity (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
> 2000 V
50 kW
Level 1
UL 94 V−0 @ 0.125 in
1344
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min Max Unit
VDD
VDD_O
VIH
VIL
IOUT
TA
Tstg
qJA
Core Supply Voltage
I/O Supply Voltage
Input High Voltage (Note 2)
Input Low Voltage
Maximum Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
− 4.6 V
− 4.6 V
− 4.6 V
−0.5 − V
− 24 mA
−40 to +85
°C
−65 to +150 °C
37 °C/W
32
qJC Thermal Resistance (Junction−to−Case) (Note 3)
11 °C/W
Tsol Wave Solder
265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum VIH is not to exceed maximum VDD.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4페이지 NB3L204K
Figure 3. Typical Phase Noise Plot at fcarrier = 156.25 MHz at an Operating Voltage of 3.3 V, Room Temperature
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The additive RMS phase
jitter contributed by the device (integrated between 12 kHz
and 20 MHz) is 45.7 fs.
The additive RMS phase jitter performance of the fanout
buffer is highly dependent on the phase noise of the input
To obtain the most accurate additive phase noise
measurement, it is vital that the source phase noise be
notably lower than that of the DUT. If the phase noise of the
source is similar or greater than the device under test output,
the source noise will dominate the additive phase jitter
calculation and lead to an artificially low result for the
additive phase noise measurement within the integration
range.
source.
Additive RMS phase jitter + ǸRMS phase jitter of output2 * RMS phase jitter of input2
45.7 fs + Ǹ73.7 fs2 * 57.8 fs2
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부품번호 | 상세설명 및 기능 | 제조사 |
NB3L204K | Differential 1:4 HCSL Fanout Buffer | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |