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BD8143MUV PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BD8143MUV
기능 High-precision Gamma Correction IC
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BD8143MUV 데이터시트, 핀배열, 회로
Power Supply IC Series for TFT LCD Panels
High-precision
Gamma Correction IC with built-in DAC
BD8143MUV
No.09035EBT08
Description
This gamma correction voltage generation IC feature built-in DACs and provide a 1chip solution with setting control via serial
communications, a high-precision 10-bitDAC, and Buffer Amp (12ch).
Features
1) 1chip design means fewer components
2) Built-in 10bit DAC
3) DAC output Buffer AMP (12ch)
4) Amp input select (CTL)
5) 3-line serial interface control
6) Thermal shut down
7) Power ON Reset Circuit
8) VQFN032V5050 Package
Applications
These ICs can be used with TFT LCD Panels used by Large-Screen and High-Definition LCD TVs.
Absolute maximum ratings (Ta=25)
Parameter
Symbol
Limit
Power Supply Voltage 1
DVCC
7
Power Supply Voltage 2
VCC
20
REFIN Voltage
Amplifier Drive Current
REF
Io
20
30 *1
Junction Temperature
Power Dissipation
Tjmax
Pd
150
2440 *2
Operating Temperature Range
Topr -40+105
Storage Temperature Range
Tstg -55+150
*1 Pd, should not be exceeded.
*2 Reduced by 19.52mW/°C over 25°C, when mounted on a glass epoxy board.
(4-layer 74.2×74.2×1.6mm).
Unit
V
V
V
mA
mW
Operating Condition (Ta=-40℃~105)
Parameter
Power Supply Voltage 1
Power Supply Voltage 2
REFIN Voltage
AMP0 Drive Current
AMP110 Drive Current
AMP11 Drive Current
Serial CLK Frequency
OSC Frequency
Symbol
DVCC
VCC
REF
IOA
IOB
IOC
fCLK
FOSC
Limit
MIN MAX
2.3 5.5
8 18
8 18
-40 -
-20 20
- 40
-5
- 200
Unit
V
V
V
mA
mA
mA
MHz
kHz
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
1/10
2009.07 - Rev.B




BD8143MUV pdf, 반도체, 판매, 대치품
BD8143MUV
Technical Note
Block Operation
REG
REG amplifiers the voltage applied to REFIN by 0.5x and output it to the VDAC pin. Connect a 1µF phase compensation
capacitor to the VDAC pin.
DAC Control
DAC Control convents the 10-bit digital signal read to the register to a voltage.
Amp
Amp amplifiers the voltage output from DAC Control by 2x. Input includes sample & hold function, refreshed by OSC.
OSC
The OSC generates the frequency that determines the Amp's refresh time.
External input can be selected using serial input.
Power On Reset
When the digital power supply DVCC is activated, each IC generates a reset signal to initialize the serial interface, registers.
Adding a 1,000 pF capacitor to the CT pin ensures that reset operation can be performed reliably, without regard to the
speed with which the power supply starts up.
VREF
This block generates the internal reference voltage.
TSD(Thermal Shut Down)
The TSD circuit turns output off when the chip temperature reaches or exceeds approximately 175°C(TYP) in order to
prevent thermal destruction or thermal runaway. When the chip returns to a specified temperature, the circuit resets.
The TSD circuit is designed only to protect the IC itself. Application thermal design should ensure operation of the IC
below the thermal shutdown junction temperature of approximately 150°C(TYP).
CTL
CTL signal can select Amp input. If CTL=”L”, each output voltage is fixed at REFIN voltage divided 13th equality.
IF CTL=”H”, each Amp input connect DAC output, and each output comply with each register.
Register
A serial signal (consisting of 10-bit gamma correction voltage values) input using the serial interface is held for each
register address. Data is initialized by the reset signal generated during a power-on reset.
Serial I/F
The serial interface uses a 3-line serial data format (LATCH, CLK, SDIN). It is used to set gamma correction voltages,
specify register addresses, and select OSC I/O.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
4/10
2009.07 - Rev.B

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BD8143MUV 전자부품, 판매, 대치품
BD8143MUV
Technical Note
Data writing time for register
Data writing time for register depend on frequency of CLK. Below formula shows data writing time for all registers.
(Because data writing time for a register is needed at 17bit data + LATCH “H” time.)
18 CLK ×
1
fCLK [MHz]
×12ch
[µs]
Refresh time of Amp input
Each Amp input have sample & hold function refreshed by OSC frequency (fosc).
Below formula shows refresh cycle.
1
fOSC [kHz]
×12ch
[µs]
When internal OSC mode, fOSC=100kHz (Typ).
Function of selecting Amp input
This IC can select Amp input by CTL signal. If CTL=”L”, Amp input is connected to resistance division of REFIN voltage.
IF CTL=”H”, connected to DAC output. When VCC(REFIN) supplies with CTL=”L”, it is possible to start up without opposite
Voltage of each output. Then, if the CTL signal changes “H” after 1ms and over since VCC(REFIN) supplied and data send
finished, start up sequence should be below Fig.
(*Amp input is connected to DAC output not only by CTL=”H”, but also DATA=1010100000(2A0h) sended to Register 12.
Also in this case, please send DATA=1010100000(2A0h) to Register 12 after 1ms and over since VCC(REFIN) supplied
And output data send finished, at this time CTL=”L”.)
REFIN
Preset value
VDAC
DAC
Control
VCC
x2 OUT
DAC value
CTL
Fig.6 Selecting Amp input block diagram
VCC
CTL
OUT0
OUT1
OUT2
Preset value
OUT10
OUT11
DAC value
Fig.7 Start up sequence
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
7/10
2009.07 - Rev.B

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BD8143MUV

High-precision Gamma Correction IC

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