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8T49N1012 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8T49N1012
기능 Frequency Synthesizer
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8T49N1012 데이터시트, 핀배열, 회로
FemtoClock® NG 12-Output
Frequency Synthesizer
8T49N1012
Datasheet
General Description
The 8T49N1012 has one fractional-feedback PLL that can be used
for frequency synthesis. It is equipped with two integer and eight
fractional output dividers, allowing the generation of up to ten
different output frequencies, ranging from 8kHz to 1GHz. Eight of
these frequencies are completely independent of each other and the
inputs. Two more are related frequencies. The twelve outputs may
select among LVPECL, LVDS, HSCL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
synthesis application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates.
The device supports Output Enable inputs and Lock and LOS status
outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Applications
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
Gigabit and Terabit IP switches / routers
Wireless base station baseband
Data communications
Features
<350fs RMS typical jitter (including spurs), @122.88MHz (12kHz
to 20MHz)
Operating modes: locked to input signal and free-run
Operates from a 10MHz to 40MHz fundamental-mode crystal
Accepts one LVPECL, LVDS, LVHSTL, HCSL or LVCMOS input
clock
Accepts frequencies ranging from 10MHz up to 600MHz
Clock input monitoring
Generates 12 LVPECL / LVDS / HSCL or 24 LVCMOS output
clocks
Output frequencies ranging from 8kHz up to 1.0GHz (Q[8:11],
Differential)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Two Output Enable control inputs
Lock and Loss-of-Signal status outputs
Programmable output de-skew adjustments in steps as small as
16ps
Register programmable through I2C or via external I2C EEPROM
Bypass clock paths and Reference Output for system tests
Power supply modes:
VCC
3.3V
/ VCCA
/ 3.3V
/
/
3V.C3CVO
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 72QFN, lead-free RoHs (6)
©2016 Integrated Device Technology, Inc.
1
October 28, 2016




8T49N1012 pdf, 반도체, 판매, 대치품
8T49N1012 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions1
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Name
REF_OUT
VCCA
OSCI
OSCO
LOCK
VCCO10
Q11
nQ11
Q10
nQ10
nc
Rsvd
VCCO8
Q9
nQ9
Q8
nQ8
Rsvd
SA1
VCCD
SCLK
SDATA
VEE
VCC
nc
nc
VCCO7
Q7
nQ7
nc
OE0
nc
Q6
nQ6
VCCO6
OE1
nQ3
Q3
Type
Output
Power
Input
Output
Output
Power
Output
Output
Output
Output
Unused
Reserved
Power
Output
Output
Output
Output
Reserved
Input
Power
I/O
I/O
Power
Power
Unused
Unused
Power
Output
Output
Unused
Input
Unused
Output
Output
Power
Input
Output
Output
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Description
Single-ended REF output. 1.8V LVCMOS/LVTTL interface levels.
Core analog functions supply pin.
Crystal Input. Accepts a 10MHz-40MHz reference from a clock oscillator or a
12pF fundamental mode, parallel-resonant crystal.
Crystal Output. This pin should be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
PLL lock indicator. LVCMOS/LVTTL interface levels.
Output supply for Q10 and Q11 output clock pairs.
Output Clock 11. Refer to the Output Drivers section for more details.
Output Clock 11. Refer to the Output Drivers section for more details.
Output Clock 10. Refer to the Output Drivers section for more details.
Output Clock 10. Refer to the Output Drivers section for more details.
No internal connection.
Reserved - leave unconnected.
Output supply for Q8 and Q9 output clock pairs.
Output Clock 9. Refer to the Output Drivers section for more details.
Output Clock 9. Refer to the Output Drivers section for more details.
Output Clock 8. Refer to the Output Drivers section for more details.
Output Clock 8. Refer to the Output Drivers section for more details.
Reserved - leave unconnected.
I2C lower address bit A1.
Core Digital functions supply voltage.
I2C interface bi-directional Clock.
I2C interface bi-directional Data.
Negative supply voltage.
Core functions supply voltage.
No internal connection.
No internal connection.
Output supply for Q7 output clock pair.
Output Clock 7. Refer to the Output Drivers section for more details.
Output Clock 7. Refer to the Output Drivers section for more details.
No internal connect.
Output enable. LVCMOS/LVTTL interface levels.
No internal connection.
Output Clock 6. Refer to the Output Drivers section for more details.
Output Clock 6. Refer to the Output Drivers section for more details.
Output supply for Q6 output clock pair.
Output enable. LVCMOS/LVTTL interface levels.
Output Clock 3. Refer to the Output Drivers section for more details.
Output Clock 3. Refer to the Output Drivers section for more details.
©2016 Integrated Device Technology, Inc.
4
October 28, 2016

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8T49N1012 전자부품, 판매, 대치품
8T49N1012 Datasheet
Principles of Operation
The 8T49N1012 accepts either a crystal input or a differential input
clock. It generates up to twelve output clocks ranging from 8kHz up
to 1.0GHz.
The 8T49N1012 has one fractional-feedback PLL that tracks either a
crystal or input reference clock. From the output of the PLL a wide
range of output frequencies can be simultaneously generated.
The device monitors the input clock and generates an alarm when an
input clock or crystal failure is detected.
The PLL provides a frequency reference that is unrelated to the input
clock or crystal frequency. The PLL frequency may be used by any of
eight fractional output dividers or two Integer output dividers to
generate up to 10 different frequencies on the twelve outputs.
The device supports programmable skew adjustment on the eight
fractional output dividers.
The device is programmable through an I2C interface and may also
autonomously read its register settings from an internal One-Time
Programmable (OTP) memory or an external serial I2C EEPROM.
Bypass Path and Reference Output
For system test purposes, the PLL may be bypassed. When
PLL_BYP is asserted the PLL input reference will be presented on
the Q0 - Q3 outputs. Note that this frequency represents the selected
input frequency after the pre-scaler circuit.
Additionally, the input reference clock or crystal frequency may be
enabled on the REF_OUT pin. This is the selected input frequency
before the pre-scaler circuit. Note that since REF_OUT is an
LVCMOS output, it is limited to 250MHz. If the selected input
frequency is higher than this, REF_OUT must be disabled.
Input Clock Selection and Pre-Scaling
The 8T49N1012 is referenced either to a fundamental mode crystal
in the range of 10MHz to 40MHz or to an input reference clock with
frequency ranging from 10MHz up to 600MHz. The reference clock
input can accept LVPECL, LVDS, LVHSTL, HCSL or LVCMOS inputs
using 1.8V, 2.5V or 3.3V logic levels. To use LVCMOS inputs, please
refer to the Application Note later in this datasheet, Wiring the
Differential Input to Accept Single-Ended Levels (page 37) for biasing
instructions.
The input reference clock does not support transmission of
spread-spectrum clocking sources. Since this family is intended for
high-performance applications, it will assume input reference
sources to have stabilities of +100ppm or better.
The user selects via the CLK_SEL input pin whether the crystal
(CLK_SEL = HIGH) or the CLK/nCLK (CLK_SEL = LOW) is used as
the reference frequency. The CLK_SEL input has an internal pull-up
so that if it is not connected, the crystal will be selected as the source.
The output of this selection logic may be monitored via the REF_OUT
pin.
Whichever source is selected is passed to a pre-scaler function
which can multiply that frequency by a factor of 2, pass it on directly
or divide it by 2 or by 4. For best performance, this pre-scaler should
be set to provide the highest frequency less than the 150MHz limit
the PLL can accept. This scaled reference may be monitored on the
Q[0:3] outputs by use of the PLL_BYP pin or via register control.
Input Clock Monitor
The PLL input (after pre-scaling) is monitored for Loss of Signal
(LOS). If no activity has been detected by the PLL on its input within
64 clock periods then the input is considered to have failed and the
internal Loss-of-Signal status flag is set and the LOS pin is asserted.
Once a LOS on the selected input reference is detected, the internal
LOS alarm will be asserted and it will remain asserted until that PLL
input clock returns.
Note that the internal LOS alarm register bit is ‘sticky’. Once asserted
it will remain asserted until a ‘1’ has been written to that register bit to
clear it. If the LOS condition is still in effect when the ‘sticky’ bit is
cleared, then it will immediately re-assert.
The LOS pin is not ‘sticky’ and will directly reflect the current LOS
status of the selected input reference.
Loop Bandwidth & Lock Indication
The 8T49N1012 has a fixed loop bandwidth set using internal
components of approximately 200kHz.
Once the PLL has locked to the selected input reference, then the
internal LOCK status will be set.
The internal lock status will be reflected directly on the LOCK pin and
on the internal LOCK status register.
Note that the internal LOCK status register bit is ‘sticky’. Once
asserted it will remain asserted until a ‘1’ has been written to that
register bit to clear it. If the LOCK condition is still in effect when the
‘sticky’ bit is cleared, then it will immediately re-assert.
©2016 Integrated Device Technology, Inc.
7
October 28, 2016

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부품번호상세설명 및 기능제조사
8T49N1012

Frequency Synthesizer

Integrated Device Technology
Integrated Device Technology

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