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PDF 8T73S208 Data sheet ( Hoja de datos )
| Número de pieza | 8T73S208 | |
| Descripción | Differential LVPECL Clock Divider and Fanout Buffer | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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2.5 V, 3.3 V Differential LVPECL
Clock Divider and Fanout Buffer
8T73S208
Datasheet
General Description
The 8T73S208 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208 ideal for those clock distribution
applications demanding well-defined performance and repeatability.
The integrated input termination resistors make interfacing to the
reference source easy and reduce passive component count. Each
output can be individually enabled or disabled in the high-impedance
state controlled by a I2C register. On power-up, all outputs are
enabled.
Features
• One differential input reference clock
• Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
• Integrated input termination resistors
• Eight LVPECL outputs
• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum input clock frequency: 1000MHz
• LVCMOS interface levels for the control inputs
• Individual output enable/disabled by I2C interface
• Output skew: 15ps (typical)
• Output rise/fall times: 350ps (maximum)
• Low additive phase jitter, RMS: 0.182ps (typical)
• Full 2.5V and 3.3V supply voltages
• Lead-free (RoHS 6) 32-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
IN
nIN
50
fREF
÷1, ÷2,
÷4, ÷8
50
VT
FSEL[1:0]
Pulldown (2)
2
SDA Pullup
I2C
SCL Pullup
8
ADR[1:0] Pulldown (2)
2
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
FSEL1
IN
VT
nIN
VCC
SDA
SCL
ADR0
24 23 22 21 20 19 18 17
25 16
26 15
27 14
28 13
8T73S208
29 12
30 11
31 10
32 9
12345678
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
Q7
nQ7 32-pin, 5mm x 5mm VFQFN
©2016 Integrated Device Technology, Inc.
1
Revision D, June 15, 2016
1 page  
8T73S208 Datasheet
Table 4C. DC Characteristics, VCC = VCCO = 2.5V ± 5% or 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VIN Input Voltage Swing1
0.15
VIH
Input
High Voltage
IN, nIN
VIN<=1V
1.2
Maximum
VCC
VIH
Input
High Voltage
IN, nIN
VIN>1V
1.4
VCC
VIL
Input
Low Voltage
IN, nIN
0 VIH – 0.15
VDIFF_IN
Differential Input Voltage
Swing
0.3
RIN
RIN_DIFF
Input Resistance IN, nIN
Differential Input
Resistance
IN, nIN
IN to VT
IN to nIN, VT = open
40 50 60
80 100 120
NOTE 1. Refer to Parameter Measurement Information, Input Voltage Swing diagram.
Units
V
V
V
V
V
Table 4D. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VOH Output High Voltage1
VOL Output Low Voltage1
VCCO – 1.102
VCCO – 1.802
VCCO – 0.95
VCCO – 1.6
VSWING
Peak-to-Peak
Output Voltage Swing
0.60 0.65
NOTE 1. Outputs terminated with 50 to VCCO – 2V.
Maximum
VCCO – 0.775
VCCO – 1.367
1.00
Units
V
V
V
Table 4E. LVPECL DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VOH Output High Voltage1
VOL Output Low Voltage1
VCCO – 1.125
VCCO – 1.799
VCCO – 0.95
VCCO – 1.6
VSWING
Peak-to-Peak Output
Voltage Swing
0.60 0.65
NOTE 1. Outputs terminated with 50 to VCCO – 2V.
Maximum
VCCO – 0.767
VCCO – 1.359
1.00
Units
V
V
V
©2016 Integrated Device Technology, Inc.
5
Revision D, June 15, 2016
5 Page 
8T73S208 Datasheet
2.5V LVPECL Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both signals must meet the VIN
and VIH input requirements. Figures 5A to 5D show interface
examples for the IN/nIN with built-in 50 termination input driven by
the most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
2.5V
LVPECL
Zo = 50
Zo = 5
R1
18
2.5V
IN
VT
nIN
V_REF_AC
Figure 5A. IN/nIN Input with Built-In 50
Driven by an LVDS Driver
Figure 5B. IN/nIN Input with Built-In 50
Driven by an LVPECL Driver
Figure 5C. IN/nIN Input with Built-In 50
Driven by a CML Driver
Figure 5D. IN/nIN Input with Built-In 50 Driven by a
CML Driver with Built-In 50 Pullup
©2016 Integrated Device Technology, Inc.
11
Revision D, June 15, 2016
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 8T73S208.PDF ] | |
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