8T73S208 PDF 데이터시트 ( Data ) - Integrated Device Technology

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8T73S208 기능

기능

Differential LVPECL Clock Divider and Fanout Buffer

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2.5 V, 3.3 V Differential LVPECL

Clock Divider and Fanout Buffer

8T73S208

Datasheet

General Description

The 8T73S208 is a high-performance differential LVPECL clock

divider and fanout buffer. The device is designed for the frequency

division and signal fanout of high-frequency, low phase-noise clocks.

The 8T73S208 is characterized to operate from a 2.5V and 3.3V

power supply. Guaranteed output-to-output and part-to-part skew

characteristics make the 8T73S208 ideal for those clock distribution

applications demanding well-defined performance and repeatability.

The integrated input termination resistors make interfacing to the

reference source easy and reduce passive component count. Each

output can be individually enabled or disabled in the high-impedance

state controlled by a I2C register. On power-up, all outputs are

enabled.

Features

• One differential input reference clock

• Differential pair can accept the following differential input

levels: LVDS, LVPECL, CML

• Integrated input termination resistors

• Eight LVPECL outputs

• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8

• Maximum input clock frequency: 1000MHz

• LVCMOS interface levels for the control inputs

• Individual output enable/disabled by I2C interface

• Output skew: 15ps (typical)

• Output rise/fall times: 350ps (maximum)

• Low additive phase jitter, RMS: 0.182ps (typical)

• Full 2.5V and 3.3V supply voltages

• Lead-free (RoHS 6) 32-Lead VFQFN packaging

• -40°C to 85°C ambient operating temperature

Block Diagram

Pin Assignment

nIN

50

fREF

÷1, ÷2,

÷4, ÷8

50

FSEL[1:0]

Pulldown (2)

SDA Pullup

I2C

SCL Pullup

ADR[1:0] Pulldown (2)

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

FSEL1

nIN

VCC

SDA

SCL

ADR0

24 23 22 21 20 19 18 17

25 16

26 15

27 14

28 13

8T73S208

29 12

30 11

31 10

32 9

12345678

nQ5

nQ4

nQ3

nQ2

nQ7 32-pin, 5mm x 5mm VFQFN

Revision D, June 15, 2016

8T73S208 Datasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC

Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Supply Voltage, VCC

Inputs, VI

Input Termination Current, IVT

Outputs, IO (LVPECL)

Continuous Current

Surge Current

Package Thermal Impedance, JA

Storage Temperature, TSTG

Maximum Junction Temperature, TJMAX

ESD - Human Body Model1

ESD - Charged Device Model1

Rating

4.6V

-0.5V to VCC + 0.5V

±35mA

50mA

100mA

42.7°C/W (0 mps)

-65C to 150C

125°C

2000V

500V

NOTE 1. According to JEDEC/JS-001-2012-KJESD22- 22-C101E.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VCC = VCCO = 2.5V ± 5% or 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum Units

VCC

VCCO

IEE

Power Supply Voltage

Output Supply Voltage

Power Supply Current

2.375

3.135

2.375

3.135

2.5V

3.3V

2.5V

3.3V

2.625

3.465

2.625

3.465

Table 4B. LVCMOS/LVTTL Input DC Characteristics, VCC = VCCO = 2.5V ± 5% or 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum Units

VIH Input High Voltage

2.2

VIL Input Low Voltage

-0.3

IIH

Input High

Current

FSEL[1:0],

ADR[1:0]

VCC = VIN = 2.625 or 3.465V

SCL, SDA

VCC = VIN = 2.625 or 3.465V

IIL

Input Low

Current

FSEL[1:0],

ADR[1:0]

VCC = 2.625 or 3.465V, VIN = 0V

-10

SCL, SDA

VCC = 2.625 or 3.465V, VIN = 0V

-150

VCC + 0.3

0.8

150

µA

Revision D, June 15, 2016

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8T73S208 Datasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

Typical Phase Jitter at 156.25MHz

Additive Phase Jitter @ 156.25MHz

12kHz to 20MHz = 0.182ps (typical)

Offset from Carrier Frequency (Hz)

The input source is 156.25MHz Wenzel Oscillator.

Revision D, June 15, 2016

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8T73S208의 기능 및 특징 중 하나는 "Differential LVPECL Clock Divider and Fanout Buffer" 입니다.

일반적으로, Integrated Device Technology에서 제조되는 전자부품들은 우수한 성능과
품질에 대한 신뢰성을 갖추고 있습니다.

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부품번호	상세설명 및 기능	제조사
8T73S208	Differential LVPECL Clock Divider and Fanout Buffer	Integrated Device Technology
8T73S208A-01	LVPECL Clock Divider and Buffer	IDT

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