8T73S1802 PDF 데이터시트 ( Data ) - Integrated Device Technology

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8T73S1802 기능

기능

1:2 Clock Fanout Buffer and Frequency Divider

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1:2 Clock Fanout Buffer and Frequency Divider 8T73S1802

DATA SHEET

General Description

Features

The 8T73S1802 is a fully integrated clock fanout buffer and frequency

divider. The input signal is frequency-divided and then fanned out to

one differential LVPECL and one LVCMOS output. Each of the

outputs can select its individual divider value from the range of ÷1,

÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and SEL1 (3-level

logic) are available to select the frequency dividers and the output

enable/disable state. The single-ended LVCMOS output is

phase-delayed by 650ps to minimize coupling of LVCMOS switching

into the differential output during its signal transition.

The 8T73S1802 is optimized to deliver very low phase noise clocks.

The VBB output generates a common-mode voltage reference for the

differential clock input so that connecting the VBB pin to an unused

input (nCLK) enables to use of single-ended input signals. The

extended temperature range supports wireless infrastructure,

telecommunication and networking end equipment requirements.

The 8T73S1802 can be used with a 3.3V or a 2.5V power supply. The

device is a member of the high-performance clock family from IDT.

• High-performance fanout buffer clock and fanout buffer

• Input clock signal is distributed to one LVPECL and one LVCMOS

output

• Configurable output dividers for both LVPECL and LVCMOS

outputs

• Supports clock frequencies up to 1000MHz (LVPECL) and up to

200MHz (LVCMOS)

• Flexible differential input supports LVPECL, LVDS and CML

• VBB generator output supports single-ended input signal

applications

• Optimized for low phase noise

• 650ps delay between LVCMOS and LVPECL minimizes coupling

between outputs

• Supply voltage: 3.3V or 2.5V

• -40°C to 85°C ambient operating temperature

• 16 VFQFN package (3mm x 3mm)

8T73S1802 REVISION 1 08/31/15

8T73S1802 DATA SHEET

Principles Of Operation

Control Pins

Operation Modes

The control input pins SEL0, SEL1 and EN are 3-level inputs with

internal 60k resistors that pull the input to the VCC level when left

open. Each input has three logic states: low (0), mid (VCC/2) and high

(1). Connect a control input to GND for achieving the low (0) state. For

the high (1) state, connect the input to VCC or leave the input open.

For the mid state, connect an external 60k resistor from the input to

GND. See Table 4D for the 3-state input min and max levels.

The device offers a many combinations of divider values and output

enable states. See Table 3 for the supported modes.

Table 3. Operation Modes1

Input2 3 4

Output Divider

EN SEL1 SEL0 QA (LVPECL) QB (LVCMOS)

0XX

Disabled

0 ÷4

÷4

0 MID

÷1

MID

÷2

÷8

÷1

÷2

÷1

÷2

÷4

÷8

÷1

÷2

÷8

Disable

÷4

NOTE 1. In the default state (control input left open), QA is disabled

and QB = ÷4.

NOTE 2. 0 = Low, MID = VCC/2, 1 = High; X = either 0, MID or 1.

NOTE 3. 0 = Low, MID = VCC/2, 1 = High; X = either 0, MID or 1.

NOTE 4. Unspecified EN, SEL1, SEL0 input logic states are reserved

and should not be used.

1:2 CLOCK FANOUT BUFFER AND FREQUENCY DIVIDER

REVISION 1 08/31/15

4페이지

8T73S1802 DATA SHEET

Table 4D. Single-Ended Characteristics, VCC = VCCO_QB = 3.0V to 3.465V or 2.5V±5%, TA = -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

VIH Input High Voltage1

0.9 x VCC

VIM Input Mid Voltage1

VIL Input High Voltage1

IIH Input High Current1

VCC = 3.0V to 3.465V

VCC = 2.5V ±5%

VIN = VCC

0.35 x VCC

0.4 x VCC

-0.3

0.65 x VCC

0.6 x VCC

0.1 x VCC

IIL Input Low Current1

VIN = 0V, VCC = 3.0V to 3.465V

VIN = 0V, VCC = 2.5V ±5%

-85

-62

-38

-30

VCC = 3.0V to VCC_MAX, IOH = -100µA VCCO_QB – 0.1

VOH High-Level Voltage QB

VCC = 3.0V, IOH = -6mA

2.4

VCC = 3.0V, IOH = -12mA

VCC = 3.0V to VCC_MAX, IOL = 100µA

0.1

VOL Low-Level Voltage QB

VCC = 3.0V, IOL = 6mA

0.5

VCC = 3.0V, IOL = 12mA

0.8

IOH High-Level Current QB

VCC = 3.3V, VO = 1.65V

-39

IOL Low-Level Current QB

VCC = 3.3V, VO = 1.65V

IOZ

Output Disabled Leakage

Current

VCC = VCC_MAX, VO = VCC or VO = 0V

-5

NOTE 1. Single-ended input: SEL1, SEL0, EN.

Units

µA

REVISION 1 08/31/15

7 1:2 CLOCK FANOUT BUFFER AND FREQUENCY DIVIDER

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8T73S1802의 기능 및 특징 중 하나는 "1:2 Clock Fanout Buffer and Frequency Divider" 입니다.

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부품번호	상세설명 및 기능	제조사
8T73S1802	1:2 Clock Fanout Buffer and Frequency Divider	Integrated Device Technology