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8T49N4811 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8T49N4811
기능 I2C Programmable Ethernet Clock Generator
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8T49N4811 데이터시트, 핀배열, 회로
I2C Programmable Ethernet Clock
Generator
8T49N4811
DATA SHEET
General Description
The 8T49N4811I is a highly flexible FemtoClock® NG
pin-programmable clock generator suitable for networking and
communications applications. It is able to generate five different
output frequencies with multiple copies of each. A fundamental mode
crystal, single-ended, or differential input reference may be used as
the source for the output frequency.
The use of pin-programming to select the input source / frequency,
desired output frequencies and output styles allow a single device to
be used in a wide variety of applications without the need for register
programming.
Selection pins use 3-level options to maximize flexibility while
minimizing package size. Selection is performed by tying a selection
pin high or low or by leaving it floating, eliminating the need for
passive components to drive a desired logic level.
Features
Fourth generation FemtoClock® NG technology
Generates multiple copies of 25MHz, 50MHz, 100MHz, 125MHz,
156.25MHz or 312.5MHz
Typical input frequency is 25MHz, with optional 125MHz and
156.25MHz input support
Differential outputs are pin programmable for LVDS or LVPECL
RMS phase jitter at 156.25MHz: <300fs typical
Power Supply Rejection Ratio better than -50dBc from
10k-1.5MHz at 3.3V power supply
Full 3.3V and 2.5V Supply Voltages
-40°C to +85°C ambient operating temperature
56-pin VFQFPN, lead-free (RoHS 6) packaging
Block Diagram
2.5V ±5% or 3.3V ±10%
PLL Bypass
SDATA, SCLK
IIC_ADRX_SEL
IN_SEL
XTAL_IN
fIN XTAL_OUT
DIN
nDIN
SLEW_LVCMOS
LVCMOS_CTRL
Qx_CTRL
QB_CTRL [1:0]
INPUT_DIVSEL
DIVSEL_x
100Ω
3
4
/A 0
1
OSC 0
1
fIN APLL
/B 0
1
/C 0
1
/D0
Frequency,
Output Type,
Slew Rate, &
Output Enable
Control
Input Divider
Frequency Select
/D1
Output Enable,Type, & Slew Rate Control
Bank A 1 LVPECL/LVDS
125MHz/156.25MHz/312.5MHz
Bank B 6 LVPECL/LVDS
50MHz/125MHz/156.25MHz
Bank C 2 LVPECL/LVDS
100MHz/125MHz/156.25MHz
Bank D0 1 LVPECL/LVDS
25MHz/125MHz/156.25MHz
Bank D1 1 LVCMOS
25MHz/125MHz
8T49N4811 REVISION A 3/30/15
1 ©2015 Integrated Device Technology, Inc.




8T49N4811 pdf, 반도체, 판매, 대치품
8T49N4811 DATA SHEET
Table 1. Pin Description (Continued)
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
E-PAD
QB3
nQB2
QB2
VDD_OB
nQB1
QB1
nQB0
QB0
QB_CTRL0
VDD
QA_CTRL
VDD_OA
nQA0
QA0
DIVSEL_A
QC_CTRL
VDD_OC
nQC1
QC1
nQC0
QC0
VDD_OC
GND
Output
Output
Output
Power
Output
Output
Output
Output
Input
Power
Input
Power
Output
Output
Input
Input
Power
Output
Output
Output
Output
Power
Power
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Power supply for Bank B.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Bank B Differential Output. LVDS or LVPECL output levels.
Pullup/Pulldown
Control input for bank B outputs QB0 to QB2 output type and OE status. LVCMOS
interface levels.
Power supply.
Pullup/Pulldown Control input for bank A output type and OE status. LVCMOS interface levels.
Power supply for Bank A.
Bank A Differential Output. LVDS or LVPECL output levels.
Bank A Differential Output. LVDS or LVPECL output levels.
Pullup/Pulldown Output divider selection for Bank A. LVCMOS interface levels.
Pullup/Pulldown Control input for bank C output type and OE status. LVCMOS interface levels.
Power supply for Bank C.
Bank C Differential Output. LVDS or LVPECL output levels.
Bank C Differential Output. LVDS or LVPECL output levels.
Bank C Differential Output. LVDS or LVPECL output levels.
Bank C Differential Output. LVDS or LVPECL output levels.
Power supply for Bank C.
Connect to ground; use thermal vias.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
CPD
ROUT
Power Dissipation QDO_S
Capacitance
QDO_S
Output
Impedance
QDO_S
QDO_S
Test Conditions
SCLK, SDATA
DIVSEL_x, IN_SEL, IN_SEL,
INPUT_DIVSEL, LVCMOS_CTRL,
Qx_CTRL, QB_CTRL[1:0]
PLL_BYPASS, IIC_ADRX_SEL,
Reserved, SLEW_LVCMOS
VDD = VDDO_ODS = 3.63V
VDD = VDDO_ODS = 2.625V
VDDO_ODS = 3.3V
VDDO_ODS = 2.5V
Minimum
Typical
3.5
50
58
42
50
18
16
24
30
Maximum
Units
pF
k
k
k
k
pF
pF
I2C PROGRAMMABLE ETHERNET CLOCK GENERATOR
4
REVISION A 3/30/15

4페이지










8T49N4811 전자부품, 판매, 대치품
Table 4I. Frequency Selection Register, Output
Byte 0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin #
Control Function
Vendor ID
Vendor ID
DIVSEL_A(0)
DIVSEL_A(1)
DIVSEL_B(0)
DIVSEL_B(1)
DIVSEL_C(0)
DIVSEL_C(1)
Description
Bank A Output Divider
Bank B Output Divider
Bank C Output Divider
8T49N4811 DATA SHEET
01
See DIVSEL_A Table
See DIVSEL_B Table
See DIVSEL_C Table
Default
0
0
0
0
0
0
0
0
Table 4J. Frequency Selection Register, Misc.
Byte1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin #
Control Function
DIVSEL_D0(0)
DIVSEL_D0(1)
LVCMOS_CTRL(0)
LVCMOS_CTRL(1)
INPUT_DIVSEL(0)
INPUT_DIVSEL(1)
IIC_ADRX_SEL
IIC_Pin Control
Description
Bank D0 Output Divider
01
See DIVSEL_D0 Table
Bank D1 LVCMOS Output Divider and OE See LVCMOS_CTRL Table
Input Mux Selection Frequency
Selects IIC write address
Selects external pins or IIC control
See INPUT_DIVSEL Table
DC (h)
DE (h)
external pin IIC
Default
1
1
1
1
0
0
0
0
Table 4K. Output Enable Bank A and B Register
Byte2
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin #
Control Function
nOE QA0
nOE QB0
nOE QB1
nOE QB2
nOE QB3
nOE QB4
nOE QB5
Description
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
N/A
Note: unlike the external control pins, in IIC each output is individually controlled
Table 4L. Output Enable Bank C and D. Output Type Select Register
Byte3
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin #
Control Function
nOE QC0
nOE QC1
nOE QD0
nOE QDO_S
Output Type Select QC0
Output Type Select QC1
Output Type Select QD0
Description
Output Enable
Output Enable
Output Enable
Output Enable
LVPECL/LVDS Select
LVPECL/LVDS Select
LVPECL/LVDS Select
N/A
0
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Default
0
0
0
0
0
0
0
0
Enable
Enable
Enable
Enable
LVPECL
LVPECL
LVPECL
1
Disable
Disable
Disable
Disable
LVDS
LVDS
LVDS
Default
0
0
0
0
0
0
0
REVISION A 3/30/15
7 I2C PROGRAMMABLE ETHERNET CLOCK GENERATOR

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8T49N4811

I2C Programmable Ethernet Clock Generator

Integrated Device Technology
Integrated Device Technology

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