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PDF 82P33731 Data sheet ( Hoja de datos )
| Número de pieza | 82P33731 | |
| Descripción | Synchronous Equipment Timing Source | |
| Fabricantes | Integrated Device Technology | |
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Synchronous Equipment Timing Source
for 10G/ 40G Synchronous Ethernet
82P33731
Short Form Datasheet
This is a short form datasheet and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found on
the last page.
HIGHLIGHTS
• Synchronous Equipment Timing Source (SETS) for Synchronous
Ethernet (SyncE) per ITU-T G.8264
• DPLL1 generates ITU-T G.8262 compliant SyncE clocks, Telcordia
GR-1244-CORE/GR-253-CORE, and ITU-T G.813 compliant
SONET/SDH clocks
• DPLL2 performs rate conversions for synchronization interfaces or
for other general purpose timing applications
• APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and
generates clocks with jitter <0.3 ps RMS (10 kHz to 20 MHz) for:
10GBASE-R, 10GBASE-W and 40GBASE-R
• APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to
20 MHz) for: 1000BASE-T and 1000BASE-X
• Fractional-N input dividers support a wide range of reference fre-
quencies
• Locks to 1 Pulse Per Second (PPS) references
• DPLLs, APLL1 and APLL2 can be configured from an external
EEPROM after reset
FEATURES
• Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization
interface signals per ITU-T G.703
• Differential reference inputs (IN3 to IN8) accept clock frequencies
between 1 PPS and 650 MHz
• Single ended inputs (IN9 to IN14) accept reference clock frequencies
between 1 PPS and 162.5 MHz
• Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any
clock reference input
• Reference monitors qualify/disqualify references depending on activ-
ity, frequency and LOS pins
• Automatic reference selection state machines select the active refer-
ence for each DPLL based on the reference monitors, priority tables,
revertive and non-revertive settings and other programmable settings
• Fractional-N input dividers enable the DPLLs to lock to a wide range
of reference clock frequencies including: 10/100/1000 Ethernet, 10G
Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI, and GNSS
frequencies
• Any reference inputs (IN3 to IN14) can be designated as external
sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a
selectable reference clock input
• FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses
that are aligned with the selected external input sync pulse input and
frequency locked to the associated reference clock input
• DPLL1 can be configured with bandwidths between 0.09 mHz and
567 Hz
• DPLL1 locks to input references with frequencies between 1 PPS and
650 MHz
• DPLL2 locks to input references with frequencies between 8 kHz and
650 MHz
• DPLL1 complies with ITU-T G.8262 for Synchronous Ethernet Equip-
ment Clock (EEC), and G.813 for Synchronous Equipment Clock
(SEC); and Telcordia GR-253-CORE/ GR-1244-CORE for Stratum 3
and SONET Minimum Clock (SMC)
• DPLL1 generates clocks with PDH, TDM, GSM, CPRI/OBSAI, 10/
100/1000 Ethernet and GNSS frequencies; these clocks are directly
available on OUT1
• DPLL2 generates N x 8 kHz clocks up to 100 MHz that are output on
OUT9 and OUT10
• APLL1, APLL2 and APLL3 are connected to DPLL1
• APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or
SONET/SDH frequencies
• APLL3 generates 10G Ethernet, WAN-PHY, and LAN-PHY frequen-
cies
• Any of eight common TCXO/OCXO frequencies can be used for the
System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,
24.576 MHz, 25 MHz or 30.72 MHz
• The I2C slave interface can be used by a host processor to access
the control and status registers
• The I2C master interface can automatically load a device configura-
tion from an external EEPROM after reset; APLL3 must be config-
ured via the I2C slave interface
• DPLLs can be connected to an internal composite clock generator
that outputs its 64 kHz synchronization signal on OUT8
• Differential outputs OUT3 to OUT6 output clocks with frequencies
between 1 PPS and 650 MHz
• Differential outputs OUT11 and OUT12 output clocks with frequen-
cies up to 650 MHz
• Single ended outputs OUT1, OUT2 and OUT7 output clocks with fre-
quencies between 1 PPS and 125 MHz
• Single ended outputs OUT9 and OUT10 output clocks N*8 kHz multi-
ples up to 100 MHz
• DPLL1 supports independent programmable delays for each of IN3
to IN14; the delay for each input is programmable in steps of 0.61 ns
with a range of ~±78 ns
• The input to output phase delay of DPLL1 is programmable in steps
of 0.0745 ps with a total range of ±20 s
• The clock phase of each of the output dividers for OUT1 (from
APLL1) to OUT7 is individually programmable in steps of ~200 ps
with a total range of +/-180°
• 1149.1 JTAG Boundary Scan
• 144-pin CABGA green package
APPLICATIONS
• Access routers, edge routers, core routers
• Carrier Ethernet switches
• Multiservice access platforms
• PON OLT
• LTE eNodeB
• ITU-T G.8264 Synchronous Equipment Timing Source (SETS)
• ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC)
• ITU-T G.813 Synchronous Equipment Clock (SEC)
• Telcordia GR-253-CORE/GR1244-CORE Stratum 3 Clock (S3) and
SONET Minimum Clock (SMC)
©2016 Integrated Device Technology, Inc.
1
Revision 4, March 20, 2016
1 page  
82P33731 Short Form Datasheet
2 PIN DESCRIPTION
Table 1: Pin Description
Pin No.
E1
K8
A11
K6
H1
J1
J2
K10
K9
M12
M11
L12
L11
K12
K11
J12
J11
G12
G11
Name
OSCI
MS/SL
SONET/SDH/
LOS3
RSTB
XO_FREQ0/
LOS0
XO_FREQ1/
LOS1
XO_FREQ2/
LOS2
IN1
IN2
IN3_POS
IN3_NEG
IN4_POS
IN4_NEG
IN5_POS
IN5_NEG
IN6_POS
IN6_NEG
IN7_POS
IN7_NEG
I/O Type
Description
Global Control Signal
OSCI: Crystal Oscillator System Clock
I CMOS A clock provided by a crystal oscillator is input on this pin. It is the system clock for the
device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ2
I
pull-up
CMOS
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit, controls whether the device is configured as the
Master or as the Slave. The signal level on this pin is reflected by the MASTER_SLAVE bit.
I
pull-down
I
pull-up
CMOS
CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, this pin takes on the operation of LOS3
LOS3- This pin is used to disqualify input clocks. See input clocks section for more details.
RSTB: Reset
Refer to section 2.2 reset operation for detail.
I
pull-down
CMOS
XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency.
XO_FREQ[2:0] Oscillator Frequency (MHz)
000 10.000
001 12.800
010 13.000
011 19.440
100 20.000
101 24.576
110 25.000
111 30.720
LOS0 ~ LOS2 - These pins are used to disqualify input clocks. See input clocks section for
more details. After reset, this pin takes on the operation of LOS0-LOS2
Input Clock and Frame Synchronization Input Signal
IN1: Input Clock 1
I
AMI
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
AMI input has internal 1k ohm to 1.5V termination. This pin can also be used as a frame
pulse input, and in this case a 8 kHz signal can be input on this pin.
IN2: Input Clock 2
I
AMI
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
AMI input has internal 1k ohm to 1.5V termination. This pin can also be used as a frame
pulse input, and in this case a 8 kHz signal can be input on this pin.
IN3_POS / IN3_NEG: Positive / Negative Input Clock 3
I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN4_POS / IN4_NEG: Positive / Negative Input Clock 4
I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN5_POS / IN5_NEG: Positive / Negative Input Clock 5
I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN6_POS / IN6_NEG: Positive / Negative Input Clock 6
I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN7_POS / IN7_NEG: Positive / Negative Input Clock 7
I PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
©2016 Integrated Device Technology, Inc.
5
Revision 4, March 20, 2016
5 Page 
82P33731 Short Form Datasheet
ORDERING INFORMATION
Table 2: Ordering Information
Part/Order Number
82P33731ABAG
Package
144-pin CABGA green package
Temperature
-40o to +85oC
"G" after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
©2016 Integrated Device Technology, Inc.
11
Revision 4, March 20, 2016
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 82P33731.PDF ] | |
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