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NB3N200S 데이터시트 PDF




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부품번호 NB3N200S 기능
기능 3.3 V Differential Multipoint Low Voltage M-LVDS Driver Receiver
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NB3N200S 데이터시트, 핀배열, 회로
NB3N200S
3.3 V Differential Multipoint
Low Voltage M-LVDS Driver
Receiver
Description
The NB3N200 is a pure 3.3 V supply differential Multipoint Low
Voltage (M−LVDS) line Driver and Receiver. NB3N200S is
TIA/EIA−899 compliant. NB3N200S offers the Type 1 receiver
threshold at 0.0 V.
These devices has a Type−1 receiver that detect the bus state with as
little as 50 mV of differential input voltage over a common−mode
voltage range of −1 V to 3.4 V. The Type−1 receivers have near zero
thresholds (±50 mV) and exhibit 25 mV of differential input voltage
hysteresis to prevent output oscillations with slowly changing signals
or loss of input.
NB3N200S supports Simplex or Half Duplex bus configurations.
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAM
8
NB20x
AYWW
G
1
NB20x
x
A
Y
WW
G or G
= Specific Device Code
= 0, 2, 4, 5
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Features
Low−Voltage Differential 30 W to 55 W Line Drivers and Receivers
for Signaling Rates Up to 200 Mbps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Type−1 Receivers Incorporate 25 mV of Hysteresis
Meets or Exceeds the M−LVDS Standard TIA/EIA−899 Pb−Free SOIC 8 Package
for Multipoint Data Interchange
Controlled Driver Output Voltage Transition Times for
Improved Signal Quality
−1 V to 3.4 V Common−Mode Voltage Range Allows
Data Transfer With up to 2 V of Ground Noise
Bus Pins High Impedance When Disabled or VCC
1.5 V
M−LVDS Bus Power Up/Down Glitch Free
Operating range: VCC = 3.3 ±10% V( 3.0 to 3.6 V)
Operation from –40°C to 85°C.
These are Pb−Free Devices
Applications
Low−Power High−Speed Short−Reach Alternative to
TIA/EIA−485
Backplane or Cabled Multipoint Data and Clock
Transmission
Cellular Base Stations
Central−Office Switches
Network Switches and Routers
Figure 1. Logic Diagrams
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 1
1
Publication Order Number:
NB3N200S/D




NB3N200S pdf, 반도체, 판매, 대치품
NB3N200S
Table 5. DC CHARACTERISTICS VCC = 3.3 ±10% V( 3.0 to 3.6 V), GND = 0 V, TA = −40°C to +85°C (See Notes 4, 5)
Symbol
Characteristic
Min Typ Max
DRIVER
|VAB| /
|VYZ|
D|VAB| /
D|VYZ|
VOS(SS)
DVOS(SS)
VOS(PP)
VYOC /
VAOC
Differential output voltage magnitude (see Figure 4)
Change in Differential output voltage magnitude between logic states (see Figure 4)
Steady state common mode output voltage (see Figure 5)
Change in Steady state common mode output voltage between logic states (see
Figure 5)
Peak−to−peak common−mode output voltage (see Figure 5)
Maximum steady−state open−circuit output voltage (see Figure 9)
480
−50
0.8
−50
0
650
50
1.2
50
150
2.4
VZOC /
VBOC
Maximum steady−state open−circuit output voltage (see Figure 9)
0 2.4
VP(H)
VP(L)
IIH
IIL
JIOSJ
IOZ
Voltage overshoot, low−to−high level output (see Figure 7)
Voltage overshoot, high−to−low level output (see Figure 7)
High−level input current (D, DE) VIH = 2 V
Low−level input current (D, DE) VIL = 0.8 V
Differential short−circuit output current magnitude (see Figure 6)
High−impedance state output current (driver only)
−1.4 V (VY or VZ) 3.8 V, other output at 1.2 V
−0.2 VSS
0
0
−15
1.2 VSS
10
10
24
10
IO(OFF)
Power−off output current (0 V VCC 1.5 V)
−1.4 V (VY or VZ) 3.8 V, other output at 1.2 V
−10
10
CY / CZ Output Capacitance VI = 0.4 sin(30E6πt) + 0.5 V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
3
CYZ Differential Output Capacitance VAB = 0.4 sin(30E6pt) V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
2.5
CY/Z
Output Capacitance Balance, (CY/CZ)
99 101
RECEIVER
VIT+ Positive−going Differential Input voltage Threshold (See Figure 11 & Table 8)
Type 1
Type 2
50
150
VIT− Negative−going Differential Input voltage Threshold (See Figure 11 & Table 8)
Type 1 −50
Type 2 50
VHYS Differential Input Voltage Hysteresis (See Figure 11 and Table 2)
Type 1
Type 2
25
0
VOH High−level output voltage (IOH = –8 mA
2.4
VOL Low−level output voltage (IOL = 8 mA)
0.4
IIH RE High-level input current (VIH = 2 V)
−10 0
IIL RE Low-level input current (VIL = 0.8 V)
−10 0
IOZ High−impedance state output current (VO = 0 V of 3.6 V)
−10 15
CA / CB Input Capacitance VI = 0.4 sin(30E6πt) + 0.5 V, other outputs at 1.2 V using HP4194A
impedance analyzer (or equivalent)
3
CAB Differential Input Capacitance VAB = 0.4 sin(30E6πt) V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
2.5
CA/B Input Capacitance Balance, (CA/CB)
99 101
Unit
mV
mV
V
mV
mV
V
V
V
V
uA
uA
mA
uA
uA
pF
pF
%
mV
mV
mV
V
V
mA
mA
mA
pF
pF
%
www.onsemi.com
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NB3N200S 전자부품, 판매, 대치품
NB3N200S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf1 ns, pulse frequency = 500 kHz,
duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20% tolerance.
C. R1 and R2 are metal film, surface mount, 1% tolerance, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 5. Test Circuit and Definitions for the Driver Common−Mode Output Voltage
Figure 6. Driver Short−Circuit Test Circuit
A. All input pulses are supplied by a generator having the following characteristics: tr or tf1 ns, frequency = 500 kHz,
duty cycle = 50 ±5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 7. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
www.onsemi.com
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NB3N200S

3.3 V Differential Multipoint Low Voltage M-LVDS Driver Receiver

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