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PDF NB3N201S Data sheet ( Hoja de datos )
| Número de pieza | NB3N201S | |
| Descripción | 3.3 V Differential Multipoint Low Voltage M-LVDS Driver Receiver | |
| Fabricantes | ON Semiconductor | |
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NB3N201S, NB3N206S
3.3 V Differential Multipoint
Low Voltage M-LVDS Driver
Receiver
Description
The NB3N20xS Series are pure 3.3 V supply differential Multipoint
Low Voltage (M−LVDS) line Drivers and Receivers. Devices
NB3N201S and NB3N206S are TIA/EIA−899 compliant. NB3N201S
offers the Type 1 receiver threshold at 0.0 V. NB3N206S offers the
Type 2 receiver threshold at 0.1 V.
These devices have Type−1 and Type−2 receivers that detect the bus
state with as little as 50 mV of differential input voltage over a
common−mode voltage range of −1 V to 3.4 V. The Type−1 receivers
have near zero thresholds (±50 mV) and exhibit 25 mV of differential
input voltage hysteresis to prevent output oscillations with slowly
changing signals or loss of input. Type−2 receivers include an offset
threshold to provide a detectable voltage under open−circuit, idle−bus,
and other faults conditions.
NB3N201S and NB3N206S support Simplex or Half Duplex bus
configurations.
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
8
NB20x
AYWW
G
1
NB20x
x
A
Y
WW
G or G
= Specific Device Code
= 1, 6
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
Features
• Low−Voltage Differential 30 W to 55 W Line Drivers
and Receivers for Signaling Rates Up to 200 Mbps
• Type−1 Receivers Incorporate 25 mV of Hysteresis
• Type−2 Receivers Provide an Offset (100 mV)
Threshold to Detect Open−Circuit and Idle−Bus
Conditions
• Meets or Exceeds the M−LVDS Standard TIA/EIA−899
for Multipoint Data Interchange
• Controlled Driver Output Voltage Transition Times for
Improved Signal Quality
• −1 V to 3.4 V Common−Mode Voltage Range Allows
Data Transfer With up to 2 V of Ground Noise
• Bus Pins High Impedance When Disabled or VCC ≤
1.5 V
• M−LVDS Bus Power Up/Down Glitch Free
• Operating range: VCC = 3.3 ±10% V( 3.0 to 3.6 V)
• Operation from –40°C to 85°C.
• These are Pb−Free Devices
Applications
• Low−Power High−Speed Short−Reach Alternative to
TIA/EIA−485
• Backplane or Cabled Multipoint Data and Clock
Transmission
• Cellular Base Stations
• Central−Office Switches
• Network Switches and Routers
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 1
1
Publication Order Number:
NB3N201S/D
1 page  
NB3N201S, NB3N206S
Table 5. DC CHARACTERISTICS VCC = 3.3 ±10% V( 3.0 to 3.6 V), GND = 0 V, TA = −40°C to +85°C (See Notes 4, 5)
Symbol
Characteristic
Min Typ Max
ICC
VIH
VIL
VBUS
Power Supply Current
Receiver Disabled Driver Enabled RE and DE at VCC, RL = 50 W, All others open
Driver and Receiver Disabled RE at VCC, DE at 0 V, RL = No Load, All others open
Driver and Receiver Enabled RE at 0 V, DE at VCC, RL = 50 W, All others open
Receiver Enabled Driver Disabled RE at 0 V, DE at 0 V, RL = 50 W, All others open
Input HIGH Voltage
Input LOW Voltage
Voltage at any bus terminal VA, VB, VY or VZ
13 22
14
16 24
13
2
GND
VCC
0.8
−1.4 3.8
|VID|
DRIVER
Magnitude of differential input voltage
0.05
VCC
|VAB|
D|VAB|
VOS(SS)
DVOS(SS)
Differential output voltage magnitude (see Figure 4)
Change in Differential output voltage magnitude between logic states (see Figure 4)
Steady state common mode output voltage (see Figure 5)
Change in Steady state common mode output voltage between logic states (see
Figure 5)
480
−50
0.8
−50
650
50
1.2
50
VOS(PP) Peak−to−peak common−mode output voltage (see Figure 5)
VAOC Maximum steady−state open−circuit output voltage (see Figure 9)
150
0 2.4
VBOC
VP(H)
VP(L)
IIH
IIL
JIOSJ
IOZ
IO(OFF)
Maximum steady−state open−circuit output voltage (see Figure 9)
Voltage overshoot, low−to−high level output (see Figure 7)
Voltage overshoot, high−to−low level output (see Figure 7)
High−level input current (D, DE) VIH = 2 V
Low−level input current (D, DE) VIL = 0.8 V
Differential short−circuit output current magnitude (see Figure 6)
High−impedance state output current (driver only)
−1.4 V ≤ (VA or VB) ≤ 3.8 V, other output at 1.2 V
Power−off output current (0 V ≤ VCC ≤ 1.5 V)
−1.4 V ≤ (VA or VB) ≤ 3.8 V, other output at 1.2 V
0
−0.2 VSS
0
0
−15
−10
2.4
1.2 VSS
10
10
24
10
10
RECEIVER
VIT+ Positive−going Differential Input voltage Threshold (See Figure 11 & Tables 8 and 9)
Type 1
Type 2
50
150
VIT− Negative−going Differential Input voltage Threshold (See Figure 11 & Tables 8 and 9)
Type 1 −50
Type 2 50
VHYS Differential Input Voltage Hysteresis (See Figure 11 and Table 2)
Type 1
Type 2
25
0
VOH High−level output voltage (IOH = –8 mA
2.4
VOL Low−level output voltage (IOL = 8 mA)
0.4
IIH RE High-level input current (VIH = 2 V)
−10 0
IIL RE Low-level input current (VIL = 0.8 V)
−10 0
IOZ High−impedance state output current (VO = 0 V of 3.6 V)
−10 15
CA / CB Input Capacitance VI = 0.4 sin(30E6πt) + 0.5 V, other outputs at 1.2 V using HP4194A
impedance analyzer (or equivalent)
3
CAB Differential Input Capacitance VAB = 0.4 sin(30E6πt) V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
2.5
CA/B Input Capacitance Balance, (CA/CB)
99 101
Unit
mA
V
V
V
mV
mV
V
mV
mV
V
V
V
V
uA
uA
mA
uA
uA
mV
mV
mV
V
V
mA
mA
mA
pF
pF
%
www.onsemi.com
5
5 Page 
NB3N201S, NB3N206S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 50 MHz, duty cycle = 50
±5%. CL is a combination of a 20%−tolerance, low−loss ceramic, surface−mount capacitor and fixture capacitance within 2 cm of the
D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 12. Receiver Timing Test Circuit and Waveforms
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11
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet NB3N201S.PDF ] | |
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