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PDF NB4N7132 Data sheet ( Hoja de datos )
| Número de pieza | NB4N7132 | |
| Descripción | Link Replicator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB4N7132
Link Replicator for Fibre
Channel, Gigabit Ethernet,
HDTV and SATA
Up to 1.5 Gb/s
Description
The NB4N7132 is a high performance 3.3 V Serial Link Replicator
which provides the function of serial loop replication and serial
loopback control commonly required in Fibre Channel, GbE, HDTV
and SATA applications. Other popular applications include Host Bus
Adaptors for routing between internal and external connectors, and
hot−pluggable links between redundant switch fabric cards.
IN is sent to both OUT0 and OUT1; each output is enabled by OE0
and OE1 when HIGH. OUT0 can select either IN or IN1 via the
MUX0 pin. Likewise, OUT1 can select between IN or IN0 via the
MUX1 pin. Out can select between IN0 and IN1.
In Link Replicator applications, such as the Line Card to Switch
Card links, IN is transmitted to both OUT0 and OUT1 which either
IN0 or IN1 is selected at OUT. In Host Adapter applications, IN goes
to OUT0 (an internal connector) which returns data on IN0. IN0 is
looped to OUT1 (an external connector) which returns data on IN1
and then back to the SerDes on OUT.
The NB4N7132 is packaged in a 4.7 mm x 9.7 mm TSSOP−28.
Features
• Replicates Fibre Channel, Gigabit Ethernet, HDTV, and
Serial ATA (SATA) Links
• T11 Fibre Channel Complaint at 1.0625 Gb/s
• No External Components Required
• IEEE802.3z Gigabit Ethernet Compliant at 1.25 Gb/s
• SMPTE−292M Compliant at 1.485 Gb/s
• 450 mW Maximum Power Dissipation
• Operating Range: VCC = 3.135 V to 3.465 V
• 28−pin, 4.4 mm x 9.7 mm TSSOP Package
• These are Pb−Free Devices
http://onsemi.com
28 Lead TSSOP
DT SUFFIX
CASE 948A
MARKING DIAGRAM*
NB4N
7132G
ALYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
NB4N7132
LOOP0
TX
RX
LOOP1
Figure 1. Simplified Application
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
July, 2011 − Rev. 1
1
Publication Order Number:
NB4N7132/D
1 page  
NB4N7132
0.01mF
TX+ I+
R
0.01mF
RT
TX−
R
I−
0.01mF
O1+
I1+
0.01mF RT
O1− I1−
0.01mF
O+
RX+
0.01mF
RT
O− RX−
SerDes
RX+
RX−
0.01mF
RT 0.01mF
NB4N7132
O+ I1+
O− I1−
0.01mF
RT0.01mF
NB4N7132
O1+ I+
O1− I−
0.01mF
RT 0.01mF
SerDes
TX+
R
TX−
R
“R” is 150 W for both 100 W differential or 150 W differential traces.
“RT” matches the differential impedance of the link.
Figure 5. NB4N7132 Application Interface Example
IN+/IN− Input Functionality
The differential inputs are internally biased to Y1.2 V. In
a typical application, the differential inputs are
capacitor−coupled and will swing symmetrically above and
below 1.2 V, preserving a 50% duty cycle to the outputs.
With this technique, the NB4N7132 will accept any
differential input allowing for LVPECL, CML, LVDS, and
HSTL input levels.
OUT+ / OUT− Outputs
The OUT+ and OUT− outputs of the NB4N7132 are
designed to drive differential transmission lines with
nominally 50 W or 75 W characteristic impedance. These
differential output buffers utilize positive emitter coupled
logic (PECL) architecture, but they do not require DC output
load resistors, and will operate properly with or without the
resistors.
OEx Output Enable
The NB4N7132 incorporates output enable pins, OE0 and
OE1, that work by powering down the output buffer and
associated driving circuitry. Using this approach results in
both differential outputs going HIGH, and a reduction in IDD
current of approx. 29 mA for each disabled output pair.
When OEx is LOW, outputs are disabled, OUTx+ and
OUTx− are set HIGH.
Power Supply Bypass information
A clean power supply will optimize the performance of
the device. The NB4N7132 provides separate power supply
pins for the digital circuitry (VDD) and LVPECL outputs
(VDDPn). Placing a bypass capacitor of 0.01 mF to 0.1 mF
on each VDD pin will help ensure a noise free VDD power
supply. The purpose of this design technique is to try and
isolate the high switching noise of the digital outputs from
the relatively sensitive digital core logic.
Resource Reference of Application Notes
AND8002 − Marking and Date Codes
AND8009 − ECLinPS Plus Spice I/O Model Kit
ORDERING INFORMATION
Device
Package
Shipping†
NB4N7132DTG
TSSOP−28
(Pb−Free)
50 Units / Rail
NB4N7132DTR2G
TSSOP−28
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
5
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| PDF Descargar | [ Datasheet NB4N7132.PDF ] | |
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