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BD8118FM PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BD8118FM
기능 White LED Driver IC
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BD8118FM 데이터시트, 핀배열, 회로
TECHNICAL NOTE
For LCD Panel Backlight Applications
White LED Driver IC
BD8118FM
rev. 1.50
Outline
BD8118FM is a white LED driver featuring a high input voltage range (36V MAX), an integrated step-up DC/DC converter
and four constant-current output drivers on a single chip. Brightness can be controlled by either PWM or VDAC methods.
Features
1) Input voltage range4.5 – 30 V
2) Integrated step-up DC/DC controller
3) Four integrated LED current driver channels (150 mA max. each channel)
4) Compatible with PWM light-modulation 0.38 – 99.5%)
5) Built-in protection functions (UVLO, OVP, TSD, OCP)
6) Abnormal status detection function (open)
7) HSOP-M28 package
Applications
Car navigation system backlights, small/medium-sized LCD panels, etc.
Absolute maximum ratings (Ta = 25 ͠)
Parameter
Symbol
Rating
Unit
Power supply voltage (Pin 1)
VCC 36
V
Load switch output voltage (Pin 2)
VLOADSW
36
V
LED output voltage (Pin 12,14,15,17)
VLED
36
V
FAIL output voltage (Pin 3,20)
VOL 7
V
Input voltage (Pin 5,6,10,11,24)
VIN -0.37 < VCC
V
VDAC input voltage (Pin 8)
Power Consumption
VDAC
Pd
-0.37 < VCC
2.20 ̪1
V
W
Junction temperature
Tjmax
150
͠
Operating temperature range
Topr -40+95
͠
Storage temperature range
LED maximum output current (Pin : 12,14,15,17)
Tstg
ILED
 -55+150
   150̪̪
͠
mA
̪1 IC mounted on glass epoxy board measuring 70mm×70mm×1.6mm, power dissipated at a rate of 17.6mw/͠ at temperatures above
25͠
̪2 Dispersion figures for LED maximum output current and VF are correlated. Please refer to data on separate sheet.
̪3 Amount of current per channel.
Operating conditions (Ta = 25 ͠)
Parameter
Symbol
Target value
Unit
Power supply voltage (Pin 1)
VCC 4.530
V
Oscillating frequency range
FOSC
50550
kHz
External synchronization frequency range (Pin 6) ̪̪ FSYNC
fosc550
kHz
External synchronization pulse duty range (Pin 6)
FSDUTY
4060
%
̪4 Connect SYNC to GND when not using external frequency synchronization.
̪5 Do not switch between internal and external synchronization when an external synchronization signal is input to the device.
October. 2008
ROHM Co., Ltd.




BD8118FM pdf, 반도체, 판매, 대치품
Block diagram
VCC 1
EN 24
SYNC 6
RT 26
COMP 28
SS 27
PWM 5
VDAC 8
ISET 9
Pin layout
 BD8118FM (HSOP-M28)
VCC 1
LOADSW 2
FAIL1 3
VREG 4
PWM 5
SYNC 6
GND 7
VDAC 8
ISET 9
LEDEN1 10
LEDEN2 11
LED1 12
N.C. 13
LED2 14
Fig.14
VREG
4
LOADSW
2
VREG
OSC
ISET
UVLO
TSD
OVP
25 OVP
PWM Comp
Control
Logic
OCP
ERR Amp
Soft
Start
Current driver
Driver
3 FAIL1
23 SWOUT
22 CS
7 GND
12 LED1
14 LED2
15 LED3
17 LED4
Open
Detect
21 PGND
20 FAIL2
10 11
LEDEN1 LEDEN2
Fig.13
28 COMP
27 SS
26 RT
25 OVP
24 EN
23 SWOUT
22 CS
21 PGND
20 FAIL2
19 N.C.
18 N.C.
17 LED4
16 N.C.
15 LED3
Pin function table
Pin S ymbol
F unction
1
VCC
Input power supply
2 LO ADSW F ET con nection for loa d switch
3 FA IL1 F a ilure signal output
4 VREG Internal refe rence voltage output
5 PW M PW M light modulation input
6 S YNC E xternal synchro nization signal input
7
GND
S mall-signal G ND
8 V DAC DC variable light m odulation input
9
ISE T
LED o utput cu rrent-setting resistance input
10 LE DEN1 LED output enable pin 1
11 LE DEN2 LED output enable pin 2
12 LED1 LED output 1
13 - N.C.
14 LED2 LED output 2
15 LED3 LED output 3
16 - N.C
17 LED4 LED output 4
18 - N.C.
19 - N.C.
20 FA IL2 LED o pen de tection signal output
21 P GND LED output G ND
22 CS DC/DC output current de tection input
23 SWO UT DC/DC switching output
24 EN E nable input
25
OVP
O ver-voltage dete ctio n input
26 RT O scill ation frequency-setting resistance input
27 S S S oft start time-setting capacitance input
28 CO MP E rror am pli fier output
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BD8118FM 전자부품, 판매, 대치품
Step-up DC/DC converter oscillation frequency (FOS)
The regulator’s internal triangular wave oscillation frequency can be set via a resistor connected to the RT pin (pin 26). This resistor
determines the charge/discharge current to the internal capacitor, thereby changing the oscillating frequency. Refer to the following
theoretical formula when setting RT:
fOSC =
30 ˜ 106
RT []
x α [kHz]
30 x 106 (V/A/S) is a constant (±16.6%) determined by the internal circuitry, and α is a correction factor that varies in relation to RT:
{ RT: α = 50k: 0.98, 60k: 0.985, 70k: 0.99, 80k: 0.994, 90k: 0.996, 100k: 1.0, 50k: 1.01, 200k: 1.02, 300k: 1.03, 400k: 1.04, 500k: 1.045 }
A resistor in the range of 62.6k523kis recommended. Settings that deviate from the frequency range shown below may cause
switching to stop, and proper operation cannot be guaranteed.
550K
450K
350K
250K
150K
50K
0
100 200 300 400 500 600 700 800
RT [k]
Fig.15 RT versus switching frequency
External DC/DC converter oscillating frequency synchronization (FSYNC)
Do not switch from external to internal oscillation of the DC/DC converter if an external synchronization signal is present on the
SYNC pin. When the signal on the SYNC terminal is switched from high to low, a delay of about 30 μS (typ.) occurs before
the internal oscillation circuitry starts to operate (only the rising edge of the input clock signal on the SYNC terminal is
recognized). Moreover, if external input frequency is less than the internal oscillation frequency, the internal oscillator will
engage after the above-mentioned 30 μS (typ.) delay; thus, do not input a synchronization signal with a frequency less than the
internal oscillation frequency.
Over-Current protection circuit (OCP)
Insert a current-sense resistor RCS between GND and the source of the n-MOSFET for current detection at the output of the
DC/DC converter. A low-pass filter (LPF) with a cutoff frequency of 1-2 MHz should also be inserted between the CS pin and
RCS in order to reduce switching noise. Ensure, however, that the time constant of this filter does not reduce the rise time of
the CS pin signal such that it erroneously engages the OCP function (for example, if FOSC = 300 kHz, then RLPF = 100 ,
CLPF = 1000 pF are appropriate values). Current detection is executed according to the following relation:
IOCP = VOLIMIT (0.4V) / RCS [A]
As OCP engages on a pulse-by-pulse basis, SWOUT is pulled low for only 1 cycle of FOSC when engaged. Special
consideration should be given to the design of the trace from RCS to system ground as this path conducts a significantly large
amount of current. Independent wiring to the system GND is recommended.
SWO UT
VOUT
(AC)
CS
LPF
RCS
Independent wiring to GND
IL
(500mA)
SW
Fig.16 Ripple current & voltage
Soft start (SS)
The SS-pin of this IC is for having the soft start function and disabling the LED-open detection. The soft start function operates
with the rising edge of the EN but not with the PWM, therefore keep the SS pin open. Also, note the LED-open detection is
disabled until the voltage of the SS-pin reaches to the VSS clamp voltage of 2.5V (typ.).
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BD8118FM

White LED Driver IC

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