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PDF MC54HC390A Data sheet ( Hoja de datos )
| Número de pieza | MC54HC390A | |
| Descripción | Dual 4-Stage Binary Ripple Counter | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
Dual 4-Stage Binary
Ripple Counter with
÷ 2 and ÷ 5 Sections
High–Performance Silicon–Gate CMOS
The MC54/74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of two independent 4–bit counters, each composed
of a divide–by–two and a divide–by–five section. The divide–by–two and
divide–by–five counters have separate clock inputs, and can be cascaded to
implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.
Flip–flops internal to the counters are triggered by high–to–low transitions
of the clock input. A separate, asynchronous reset is provided for each 4–bit
counter. State changes of the Q outputs do not occur simultaneously
because of internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used as clocks or strobes
except when gated with the Clock of the HC390A.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAM
1, 15
CLOCK A
÷2
COUNTER
3, 13 QA
CLOCK B 4, 12
÷5
COUNTER
5, 11
QB
6, 10
7, 9
QC
QD
2, 14
RESET
PIN 16 = VCC
PIN 8 = GND
This document contains information on a product under development. Motorola reserves the right
to change or discontinue this product without notice.
MC54/74HC390A
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
CLOCK Aa
RESET a
QAa
CLOCK Ba
QBa
QCa
QDa
GND
1
2
3
4
5
6
7
8
16 VCC
15 CLOCK Ab
14 RESET b
13 QAb
12 CLOCK Bb
11 QBb
10 QCb
9 QDb
FUNCTION TABLE
Clock
AB
Reset Action
XX
X
X
H Reset
÷ 2 and ÷ 5
L Increment
÷2
L Increment
÷5
10/95
© Motorola, Inc. 1995
1 REV 0
1 page  
MC54/74HC390A
PIN DESCRIPTIONS
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
Clock A is the clock input to the ÷ 2 counter; Clock B is the
clock input to the ÷ 5 counter. The internal flip–flops are
toggled by high–to–low transitions of the clock input.
CONTROL INPUTS
Reset (Pins 2, 14)
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip–flops, and forces QA through
QD low.
OUTPUTS
QA (Pins 3, 13)
Output of the ÷ 2 counter.
QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)
Outputs of the ÷ 5 counter. QD is the most significant bit.
QA is the least significant bit when the counter is connected
for BCD output as in Figure 4. QB is the least significant bit
when the counter is operating in the bi–quinary mode as in
Figure 5.
CLOCK
Q
tf
90%
50%
10% 10%
tw
90%
50%
10%
1/fmax
tPLH
tTLH
tr
tPHL
tTHL
SWITCHING WAVEFORMS
VCC
GND RESET
tPHL
Q
CLOCK
tw
50%
50%
trec
50%
Figure 1.
Figure 2.
VCC
GND
VCC
GND
TEST CIRCUIT
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 3.
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MC54HC390A.PDF ] | |
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