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PDF MC54HC563 Data sheet ( Hoja de datos )
| Número de pieza | MC54HC563 | |
| Descripción | Octal 3-State Inverting Transparent Latch | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Inverting
Transparent Latch
High–Performance Silicon–Gate CMOS
The MC54/74HC563 is identical in pinout to the LS563. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is identical in function to the HC533 but has the Data Inputs on
the opposite side of the package from the outputs to facilitate PC board
layout.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The data appears at the outputs
in inverted form. When Latch Enable goes low, data meeting the setup and
hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high–impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC573 is the noninverting version of this function.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 202 FETs or 50.5 Equivalent Gates
LOGIC DIAGRAM
D0 2
D1 3
D2 4
DATA D3 5
INPUTS D4 6
D5 7
D6 8
D7 9
LATCH
ENABLE
OUTPUT
ENABLE
11
1
19
Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
INVERTING
OUTPUTS
PIN 20 = VCC
PIN 10 = GND
MC54/74HC563
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
OUTPUT
ENABLE
1
D0 2
20 VCC
19 Q0
D1 3
18 Q1
D2 4
17 Q2
D3 5
16 Q3
D4 6
15 Q4
D5 7
14 Q5
D6 8
13 Q6
D7 9
GND 10
12 Q7
11 LATCH
ENABLE
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable D
Q
L HH L
L HL H
L L X No Change
H XX Z
X = don’t care
Z = high impedance
10/95
© Motorola, Inc. 1995
1 REV 6
1 page  
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
LATCH
ENABLE
11
OUTPUT
ENABLE
1
EXPANDED LOGIC DIAGRAM
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
MC54/74HC563
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC54HC563.PDF ] | |
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