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A8652 데이터시트 PDF




Allegro에서 제조한 전자 부품 A8652은 전자 산업 및 응용 분야에서
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부품번호 A8652 기능
기능 Synchronous USB Buck Regulator
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A8652 데이터시트, 핀배열, 회로
A8652, A8653
Wide Input Voltage, Synchronous USB Buck Regulator
with Remote Load Regulation
FEATURES AND BENEFITS
• Automotive AEC-Q100 qualified
• Cable and wiring drop compensation
• Dynamic voltage correction with controller
• Integrated high-side and low-side switching MOSFETs
• Programmable load-side current limit
• Maximized duty cycle for low dropout operation
• Operating input voltage range: 4 V to 36 V
• UVLO STOP threshold is at 2.6 VTYP
• Withstands surge voltages up to 40 V
• Continuous loading: 2.6 A for A8653; 1 A for A8652
• Adjustable switching frequency (fSW): 100 kHz to
2.2 MHz
• Synchronization to external clock: 100 kHz to 2.2 MHz
• Frequency dithering for lower EMI signature
• External adjustable compensation network
• Stable with ceramic output capacitors
Continued on next page...
PACKAGES:
16-Pin eTSSOP (suffix LP) with exposed thermal pad
Not to scale
DESCRIPTION
The A8652/53 is a high output current synchronous buck
regulator that provides tight load regulation over a wiring
harness without the need for remote sense lines.This remote load
regulation is achieved with an integrated open-loop correction
scheme that, given a known wiring harness resistance, adjusts
the output voltage based on the measured load current and a
user-programmable gain, achieving ±2% accuracy at 500 mV
of correction. The Remote Load Regulation control includes a
115% regulated voltage clamp in conjunction with a dynamic
overvoltage protection, with OVP threshold changing with the
correction voltage. TheA8652/53 includes a user-configurable
load-side current limit to fold back the output voltage during an
output overcurrent condition. TheA8652/53 regulates nominal
input voltages from 4 to 36 V and remains operational when
VIN drops as low as 2.6 V. When the input voltage approaches
the output voltage, the duty cycle is maximized to maintain
the output voltage.
The A8652/53 features include externally set soft-start time,
external compensation network, an EN input to enable VOUT,
a SYNC/FSET input to synchronize or set the PWM switching
APPLICATIONS
• Automotive USB Power Ports
• Rear Seat Entertainment
• Navigation Systems
• Motorcycle Clusters
Continued on next page...
VIN
CIN
VIN
2 × 4.7 µF
GND
EN
RFSET
SYNC/FSET
CSS
22 nF
SS
RZ
CP
CZ
COMP
FB
A8652/3
BOOT
SW
GADJ
CBOOT
100 nF
RGADJ
LO
CO
RSEN
VOUT
ISEN+
ISEN-
IADJ
CF
(optional)
RF
(optional)
RIADJ
POK
RPU
10 kΩ
RFB1
24.9 kΩ
RFB2
4.75 kΩ
RWIRE/2
RWIRE/2
VLOAD
CLOAD
A8652/53-DS, Rev.2
Typical Application Diagram 1




A8652 pdf, 반도체, 판매, 대치품
A8652,
A8653
Wide Input Voltage, Synchronous USB Buck Regulator
with Remote Load Regulation
PINOUT DIAGRAM AND TERMINAL LIST TABLE
EN 1
VIN 2
SS 3
GADJ 4
FB 5
IADJ 6
SGND 7
COMP 8
PAD
16 BOOT
15 SW
14 PGND
13 PGND
12 ISEN+
11 ISEN–
10 POK
9 SYNC/FSET
Package LP, 16-Pin eTSSOP Pinout Diagram
Terminal List Table
Symbol
Number
EN 1
VIN 2
SS 3
GADJ
4
FB
IADJ
SGND
COMP
SYNC/FSET
POK
ISEN–
ISEN+
PGND
SW
BOOT
PAD
5
6
7
8
9
10
11
12
13, 14
115
16
Function
Enable input. This pin is used to turn the converter on or off: set this pin high to turn the converter on or set this pin low to
turn the converter off. May be connected to VIN.
Power input for the control circuits and the drain of the internal high-side N-channel MOSFET. A high quality ceramic
capacitor should be placed very close to this pin.
Soft-Start pin. Connect a capacitor, CSS, from this pin to GND to set the soft-start time. This capacitor also determines
the hiccup period during overcurrent.
This pin is used to set the gain of the differential current sense amplifier with ISEN+/ISEN– pins. A resistor from this pin
to GND set the amplifier gain. Together with load sense resistor, it sets the desired voltage correction at the specified
load condition. Grounding GADJ disables Remote Load Regulation function.
Feedback (negative) input to the error amplifier. Connect a resistor divider from the converter output node (VOUT) to this
pin to program the output voltage.
Active current limit adjust pin. A resistor from this pin to GND sets the current limit. When the load current exceeds this
limit, the output voltage will decrease at the predefined slope.
Signal (quiet) GND.
Output of the error amplifier and compensation node for the control loop. Connect a series RC network from this pin to
GND for loop compensation.
Frequency setting and synchronization pin. A resistor, RFSET, from this pin to GND sets the PWM switching frequency.
Power OK output signal. This pin is an open-drain output that transitions from low impedance to high impedance when
the output is within the final regulation voltage and no load side current limit exists.
Negative current-sensing pin to the internal current sense amplifier, connected to the load side of the external current
sensing resistor.
Positive current-sensing pin to the internal current sense amplifier, connected to the inductor side of the external current
sensing resistor.
Power GND.
The source of the high-side N-channel MOSFET. The output inductor (LO) should be connected to this pin. LO should be
placed as close as possible to this pin and connected with relatively wide traces.
High-side gate drive boost input. Connect a 100 nF ceramic capacitor from BOOT to SW.
Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground
plane(s) of the PCB with at least 6 vias, directly in the pad.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4

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A8652 전자부품, 판매, 대치품
A8652,
A8653
Wide Input Voltage, Synchronous USB Buck Regulator
with Remote Load Regulation
ELECTRICAL CHARACTERISTICS (continued): Valid at 4 V ≤ VIN ≤ 36 V; TA = 25ºC; • indicates specifications guar-
anteed –40°C ≤ TA = TJ ≤ 150°C (unless noted otherwise).
Characteristics
Symbol
Test Conditions
Min. Typ. Max. Unit
OSCILLATOR
PWM Switching Frequency
PWM Frequency Dithering
Minimum Controllable On-Time
Minimum Switch Off-Time
FSET SYNCHRONIZATION TIMING
fSW
fDITHER
tON(MIN)
tOFF(MIN)
RFSET = 261 kΩ
RFSET = 61.9 kΩ
RFSET = 10.5 kΩ
No dithering with FSET synchronization
VIN = 12 V, IOUT = 1 A
VIN = 12 V, IOUT = 1 A
– 100 –
375 415 457
– 2000 –
– ±13 –
– 95 135
– 100 135
kHz
kHz
kHz
%
ns
ns
Synchronization Frequency Range
Synchronization Input Off-Time
Synchronization Input Rise Time3
Synchronization Input Fall Time3
Synchronization Rising Threshold
Synchronization Falling Threshold
CURRENT LOOP
fSW_MULT
tSYNC_OFF
tr(SYNC)
tf(SYNC)
VSYNC(HI)
VSYNC(LO)
VSYNC rising
VSYNC falling
100 – 2200 kHz
0.2 – 1.3 µs
– 10 15 ns
– 10 15 ns
––2 V
0.5 – 0.7 V
Peak Inductor (Pulse-by-Pulse) Current
Limit
IPK_LIM(MINON) tON = tON(MIN)
IPK_LIM(MINOFF) tON = 1/fSW – tOFF(MIN), No Sync
A8653
A8652
A8653
A8652
3.3
1.5
2.4
0.9
4 4.62
1.8 2.1
3.2 4
1 1.5
A
A
A
A
Load-Side Current Limit
IOUT_LIM
RIADJ = 20 kΩ, RSEN = 20 mΩ,
VOUT = 5 V
A8653
A8652
2.5 3 3.3
1 1.2 1.4
A
A
COMP to SW Current Gain
gmPOWER
A8653
A8652
– 6.3 – A/V
– 3.2 – A/V
Slope Compensation
RFSET = 261 kΩ, 100 kHz
RFSET = 61.9 kΩ, 415 kHz
SE
RFSET = 10.5 kΩ, 2 MHz
RFSET = 261 kΩ, 100 kHz
RFSET = 61.9 kΩ, 415 kHz
RFSET = 10.5 kΩ, 2 MHz
A8653
A8652
– 0.056 –
0.09 0.24 0.43
– 1.3 –
– 0.035 –
0.07 0.15 0.23
– 0.8 –
A/µs
A/µs
A/µs
A/µs
A/µs
A/µs
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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