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ADP7158 데이터시트 PDF




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부품번호 ADP7158 기능
기능 RF Linear Regulator
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ADP7158 데이터시트, 핀배열, 회로
Data Sheet
2 A, Ultralow Noise,
High PSRR, RF Linear Regulator
ADP7158
FEATURES
Input voltage range: 2.3 V to 5.5 V
16 standard voltages between 1.2 V and 3.3 V available
Maximum load current: 2 A
Low noise
0.9 μV rms total integrated noise from 100 Hz to 100 kHz
1.6 μV rms total integrated noise from 10 Hz to 100 kHz
Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz
Power supply rejection ratio (PSRR)
70 dB from 1 kHz to 100 kHz; 50 dB at 1 MHz, VOUT = 3.3 V,
VIN = 4.0 V
Dropout voltage: 200 mV typical at IOUT = 2 A, VOUT = 3.3 V
Initial accuracy: ±0.6% at ILOAD = 10 mA
Accuracy over line, load, and temperature: ±1.5%
Quiescent current: IGND = 4.0 mA at no load, 9.0 mA at 2 A
Low shutdown current: 0.2 μA
Stable with a 10 μF ceramic output capacitor
10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages
Precision enable
Supported by ADIsimPower tool
APPLICATIONS
Regulation to noise sensitive applications: phase-locked
loops (PLLs), voltage controlled oscillators (VCOs), and
PLLs with integrated VCOs
Communications and infrastructure
Backhaul and microwave links
GENERAL DESCRIPTION
The ADP7158 is a linear regulator that operates from 2.3 V to
5.5 V and provides up to 2 A of output current. Using an advanced
proprietary architecture, it provides high power supply rejection
and ultralow noise, achieving excellent line and load transient
response with only a 10 μF ceramic output capacitor.
There are 16 standard output voltages for the ADP7158. The
following voltages are available from stock: 1.2 V, 1.8 V, 2.0 V,
2.5 V, 2.8 V, 3.0 V and 3.3 V. Additional voltages available by
special order are 1.3 V, 1.5 V, 1.6 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V,
3.1V and 3.2 V.
The ADP7158 regulator typical output noise is 0.9 μV rms
from 100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral
density from 10 kHz to 1 MHz. The ADP7158 is available in a
10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages,
making it not only a very compact solution, but also providing
excellent thermal performance for applications requiring up to
2 A of output current in a small, low profile footprint.
TYPICAL APPLICATION CIRCUIT
VIN = 3.8V
CIN
10µF
ON
OFF
CBYP
1µF
ADP7158
VIN VOUT
VOUT_SENSE
EN
BYP
REF
REF_SENSE
VOUT = 3.3V
COUT
10µF
CREF
1µF
CREG
1µF
VREG
GND (EPAD)
Figure 1.
Table 1. Related Devices
Model
Input
Voltage
ADP7159 2.3 V to 5.5 V
ADP7156,
ADP7157
ADM7150,
ADM7151
ADM7154,
ADM7155
ADM7160
2.3 V to 5.5 V
4.5 V to 16 V
2.3 V to 5.5 V
2.2 V to 5.5 V
Output
Current
2A
Fixed/
Adj1
Adj
1.2 A
800 mA
600 mA
200 mA
Fixed/
Adj
Fixed/
Adj
Fixed/
Adj
Fixed
Package
10-lead LFCSP/
8-lead SOIC
10-lead LFCSP/
8-lead SOIC
8-lead LFCSP/
8-lead SOIC
8-lead LFCSP/
8-lead SOIC
6-lead LFCSP/
5-lead TSOT
1 Adj means adjustable.
1k
CBYP = 1µF
CBYP = 10µF
CBYP = 100µF
100 CBYP = 1000µF
10
1
0.1
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 2. Noise Spectral Density at Various Values of CBYP, VOUT = 3.3 V
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADP7158 pdf, 반도체, 판매, 대치품
Data Sheet
ADP7158
SPECIFICATIONS
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater; VEN = VIN; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF;
TA = 25°C for typical specifications; TA = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE RANGE
LOAD CURRENT
OPERATING SUPPLY CURRENT
Symbol
VIN
ILOAD
IGND
SHUTDOWN CURRENT
NOISE1
Output Noise
IIN_SD
OUTNOISE
Noise Spectral Density
OUTNSD
POWER SUPPLY REJECTION RATIO1 PSRR
OUTPUT VOLTAGE ACCURACY
Output Voltage2
Initial Accuracy
VOUT
REGULATION
Line
Load3
CURRENT-LIMIT THRESHOLD4
REF
VOUT
DROPOUT VOLTAGE5
PULL-DOWN RESISTANCE
VOUT
VREG
REF
BYP
START-UP TIME1, 6
VOUT
VREG
REF
THERMAL SHUTDOWN1
Threshold
Hysteresis
UNDERVOLTAGE THRESHOLDS
Input Voltage
Rising
Falling
Hysteresis
∆VOUT/∆VIN
∆VOUT/∆IOUT
ILIMIT
VDROPOUT
VOUT_PULL
VREG_PULL
VREF_PULL
VBYP_PULL
tSTART-UP
tREG_START-UP
tREF_START-UP
TSSD
TSSD_HYS
UVLORISE
UVLOFALL
UVLOHYS
Test Conditions/Comments
ILOAD = 0 µA
ILOAD = 2 A
EN = GND
VOUT = 1.2 V to 3.3 V
10 Hz to 100 kHz
100 Hz to 100 kHz
10 kHz to 1 MHz
1 kHz to 100 kHz, VIN = 4.0 V, VOUT = 3.3 V,
ILOAD = 2 A
1 MHz, VIN = 4.0 V, VOUT = 3.3 V, ILOAD = 2 A
1 kHz to 100 kHz, VIN = 2.6 V, VOUT = 1.8 V,
ILOAD = 2 A
1 MHz, VIN = 2.6 V, VOUT = 1.8 V, ILOAD = 2 A
ILOAD = 10 mA, TA = 25°C
10 mA < ILOAD < 2 A, TA = 25°C
10 mA < ILOAD < 2 A, TA = −40°C to +125°C
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater
to 5.5 V
IOUT = 10 mA to 2 A
IOUT = 1.2 A, VOUT = 3.3 V
IOUT = 2 A, VOUT = 3.3 V
EN = 0 V, VIN = 5.5 V
VOUT = 1 V,
VREG = 1 V
VREF = 1 V
VBYP = 1 V
VOUT = 3.3 V
TJ rising
Min Typ Max
2.3 5.5
2
4.0 8.0
9.0 14.0
0.2 4
1.6
0.9
1.7
70
50
70
50
1.2 3.3
−0.6 +0.6
−1.0 +1.0
−1.5 +1.5
−0.1 +0.1
0.3
22
2.4 3
3.8
120 170
200 280
650
31
850
650
1.2
0.6
0.5
150
15
2.22 2.29
1.95 2.02
200
Unit
V
A
mA
mA
µA
µV rms
µV rms
nV/√Hz
dB
dB
dB
dB
V
%
%
%
%/V
%/A
mA
A
mV
mV
Ω
Ω
Ω
ms
ms
ms
°C
°C
V
V
mV
Rev. A | Page 3 of 22

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ADP7158 전자부품, 판매, 대치품
ADP7158
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUT 1
VOUT 2
VOUT_SENSE 3
BYP 4
EN 5
ADP7158
TOP VIEW
(Not to Scale)
10 VIN
9 VIN
8 VREG
7 REF
6 REF_SENSE
VOUT 1
VOUT_SENSE 2
BYP 3
EN 4
ADP7158
TOP VIEW
(Not to Scale)
8 VIN
7 VREG
6 REF
5 REF_SENSE
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL
PERFORMACE, AND IT IS ELECTRICALLY CONNECTED TO
GROUND INSIDE THE PACKAGE. CONNECT THE EXPOSED
PAD TO THE GROUND PLANE ON THE BOARD TO ENSURE
PROPER OPERATION.
Figure 3. 10-Lead LFCSP Pin Configuration
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL
PERFORMACE, AND IT IS ELECTRICALLY CONNECTED TO
GROUND INSIDE THE PACKAGE. CONNECT THE EXPOSED
PAD TO THE GROUND PLANE ON THE BOARD TO ENSURE
PROPER OPERATION.
Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LFCSP SOIC
Mnemonic
1, 2 1
VOUT
32
VOUT_SENSE
43
BYP
54
EN
65
REF_SENSE
76
REF
87
VREG
9, 10 8
VIN
EP
Description
Regulated Output Voltage. Bypass VOUT to ground with a 10 μF or greater capacitor.
Output Sense. VOUT_SENSE is internally connected to VOUT with a 10 Ω resistor. Connect
VOUT_SENSE as close to the load as possible.
Low Noise Bypass Capacitor. Connect a 1 μF capacitor from the BYP pin to ground to reduce noise.
Do not connect a load to this pin.
Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
Reference Sense. Connect REF_SENSE to the REF pin. Do not connect REF_SENSE to VOUT or
ground.
Low Noise Reference Voltage Output. Bypass REF to ground with a 1 μF or greater capacitor. Short
REF_SENSE to REF for fixed output voltages. Do not connect a load to this pin.
Regulated Input Supply Voltage to Low Dropout (LDO) Amplifier. Bypass VREG to ground with a
1 μF or greater capacitor.
Regulator Input Supply Voltage. Bypass VIN to ground with a 10 μF or greater capacitor.
Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad
enhances thermal performance, and it is electrically connected to ground inside the package.
Connect the exposed pad to the ground plane on the board to ensure proper operation.
Rev. A | Page 6 of 22

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