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ADP1761 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ADP1761
기능 CMOS Linear Regulator
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ADP1761 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
1 A maximum output current
Low input voltage supply range
VIN = 1.10 V to 1.98 V, no external bias supply required
Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V
Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V
Ultralow noise: 2 μV rms, 100 Hz to 100 kHz
Noise spectral density
4 nV/√Hz at 10 kHz
3 nV/√Hz at 100 kHz
Low dropout voltage: 30 mV typical at 1 A load
Operating supply current: 4.5 mA typical at no load
±1.5% fixed output voltage accuracy over line, load, and
temperature
Excellent power supply rejection ratio (PSRR) performance
67 dB typical at 10 kHz at 1 A load
51 dB typical at 100 kHz at 1 A load
Excellent load/line transient response
Soft start to reduce inrush current
Optimized for small 10 μF ceramic capacitors
Current-limit and thermal overload protection
Power-good indicator
Precision enable
16-lead, 3 mm × 3 mm LFCSP package
APPLICATIONS
Regulation to noise sensitive applications such as radio
frequency (RF) transceivers, analog-to-digital converter
(ADC) and digital-to-analog converter (DAC) circuits,
phase-locked loops (PLLs), voltage controlled oscillators
(VCOs) and clocking integrated circuits
Field-programmable gate array (FPGA) and digital signal
processor (DSP) supplies
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP1761 is a low noise, low dropout (LDO) linear regulator. It
is designed to operate from a single input supply with an input
voltage as low as 1.10 V, without the requirement of an external
bias supply to increase efficiency and provide up to 1 A of
output current.
The low 30 mV typical dropout voltage at a 1 A load allows the
ADP1761 to operate with a small headroom while maintaining
regulation and providing better efficiency.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
1 A, Low VIN, Low Noise,
CMOS Linear Regulator
ADP1761
TYPICAL APPLICATION CIRCUITS
VIN = 1.7V
CIN
10µF
RPULL-UP
100k
PG
ADP1761
VIN VOUT
SENSE
EN
PG
SS VADJ
VOUT = 1.5V
COUT
10µF
ON
OFF
CSS
10nF
CREG
1µF
VREG
REFCAP
GND
CREF
1µF
Figure 1. Fixed Output Operation
VIN = 1.7V
CIN
10µF
RPULL-UP
100k
PG
ADP1761
VIN VOUT
SENSE
EN
PG
SS VADJ
CSS
10nF
CREG
1µF
VREG
REFCAP
GND
VOUT = 1.5V
COUT
10µF
ON
OFF
CREF
1µF
RADJ
10k
Figure 2. Adjustable Output Operation
Table 1. Related Devices
Device
Input Maximum
Voltage Current
ADP1762 1.10 V to 2 A
1.98 V
ADP1763 1.10 V to 3 A
1.98 V
ADP1740/ 1.6 V to 2 A
ADP1741 3.6 V
ADP1752/ 1.6 V to 0.8 A
ADP1753 3.6 V
ADP1754/ 1.6 V to 1.2 A
ADP1755 3.6 V
Fixed/
Adjustable
Fixed/adjustable
Fixed/adjustable
Fixed/adjustable
Fixed/adjustable
Fixed/adjustable
Package
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
The ADP1761 is optimized for stable operation with small 10 μF
ceramic output capacitors. The ADP1761 delivers optimal transient
performance with minimal board area.
The ADP1761 is available in fixed output voltages ranging from
0.9 V to 1.5 V. The output of the adjustable output model can be
set from 0.5 V to 1.5 V through an external resistor connected
between VADJ and ground.
The ADP1761 has an externally programmable soft start time by
connecting a capacitor to the SS pin. Short-circuit and thermal
overload protection circuits prevent damage in adverse conditions.
The ADP1761 is available in a small 16-lead LFCSP package for the
smallest footprint solution to meet a variety of applications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADP1761 pdf, 반도체, 판매, 대치품
Data Sheet
ADP1761
SPECIFICATIONS
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, ILOAD = 10 mA, CIN = 10 μF, COUT = 10 μF, CREF = 1 μF, CREG = 1 μF, TA = 25°C,
Minimum and maximum limits at TJ = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE SUPPLY RANGE
CURRENT
Operating Supply Current
Shutdown Current
OUTPUT NOISE1
Noise Spectral Density
POWER SUPPLY REJECTION RATIO1
OUTPUT VOLTAGE
Output Voltage Range
Fixed Output Voltage Accuracy
ADJUSTABLE PIN CURRENT
ADJUSTABLE OUTPUT VOLTAGE GAIN FACTOR
REGULATION
Line Regulation
Load Regulation2
DROPOUT VOLTAGE3
START-UP TIME1,4
SOFT START CURRENT
CURRENT-LIMIT THRESHOLD5
Symbol
VIN
Test Conditions/Comments
TJ = −40°C to +125°C
IGND
IGND-SD
OUTNOISE
OUTNSD
PSRR
ILOAD = 0 μA
ILOAD = 10 mA
ILOAD = 100 mA
ILOAD = 1 A
EN = GND
TJ = −40°C to +85°C,
VIN = (VOUT + 0.2 V) to 1.98 V
TJ = 85°C to 125°C,
VIN = (VOUT + 0.2 V) to 1.98 V
10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V
100 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V
10 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V
100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V
10 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V
100 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V
VOUT = 0.9 V to 1.5 V, ILOAD = 100 mA
At 10 kHz
At 100 kHz
ILOAD = 1 A, modulated VIN
10 kHz, VOUT = 1.3 V, VIN = 1.5 V
100 kHz, VOUT = 1.3 V, VIN = 1.5 V
1 MHz, VOUT = 1.3 V, VIN = 1.5 V
10 kHz, VOUT = 0.9 V, VIN = 1.1 V
100 kHz, VOUT = 0.9 V, VIN = 1.1 V
1 MHz, VOUT = 0.9 V, VIN = 1.1 V
VOUT_FIXED
VOUT_ADJ
VOUT
IADJ
AD
TA = 25°C
ILOAD = 100 mA, TA = 25°C
10 mA < ILOAD < 1 A, VIN = (VOUT + 0.2 V) to
1.98 V, TJ = 0°C to 85°C
10 mA < ILOAD < 1 A, VIN = (VOUT + 0.2 V) to
1.98 V
TA = 25°C
VIN = (VOUT + 0.2 V) to 1.98 V
TA = 25°C
VIN = (VOUT + 0.2 V) to 1.98 V
∆VOUT/∆VIN
∆VOUT/∆IOUT
VDROPOUT
TSTART-UP
ISS
ILIMIT
VIN = (VOUT + 0.2 V) to 1.98 V
ILOAD = 10 mA to 1 A
ILOAD = 100 mA, VOUT = 1.2 V
ILOAD = 1 A, VOUT = 1.2 V
CSS = 10 nF, VOUT = 1.3 V
1.1 V ≤ VIN ≤ 1.98 V
Min Typ Max Unit
1.10 1.98 V
4.5 8
4.9 8
5.5 8.5
7.3 11
2
180
800
12
2
15
2
21
2
mA
mA
mA
mA
μA
μA
μA
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
4 nV/√Hz
3 nV/√Hz
67 dB
51 dB
41 dB
66 dB
50 dB
35 dB
0.9 1.5 V
0.5 1.5 V
−0.5 +0.5 %
−1 +1.5 %
−1.5 +1.5 %
49.5 50.0 50.5 μA
48.8 50.0 51.0 μA
3.0
2.95 3.055
−0.15
+0.15 %/V
0.25 0.44 %/A
12 23 mV
30 53 mV
0.6 ms
8 10 12 μA
1.5 2 2.4 A
Rev. 0 | Page 3 of 18

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ADP1761 전자부품, 판매, 대치품
ADP1761
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
VIN 1
VIN 2
VIN 3
VIN 4
ADP1761
TOP VIEW
(Not to Scale)
12 VOUT
11 VOUT
10 VOUT
9 VOUT
NOTES
1. THE EXPOSED PAD IS ELECTRICALLY
CONNECTED TO GND. IT IS RECOMMENDED
THAT THIS PAD BE CONNECTED TO A GROUND
PLANE ON THE PCB. THE EXPOSED PAD IS
ON THE BOTTOM OF THE PACKAGE.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4 VIN
Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor. Note that all four VIN pins must be
connected to the source supply.
5
REFCAP
Reference Filter Capacitor. Connect a 1 μF capacitor from the REFCAP pin to ground. Do not connect a load to
ground.
6 VREG
Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not connect
a load to ground.
7 GND
Ground.
8 VADJ
Adjustable Voltage Pin for the Adjustable Output Option. Connect a 10 kΩ external resistor between the VADJ
pin and ground to set the output voltage to 1.5 V. For the fixed output option, leave this pin floating.
9 to 12 VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor. Note that all four VOUT pins
must be connected to the load.
13 SENSE
Sense Input. The SENSE pin measures the actual output voltage at the load and feeds it to the error amplifier.
Connect VSENSE as close to the load as possible to minimize the effect of IR voltage drop between VOUT and the load.
14 SS
Soft Start Pin. A 10 nF capacitor connected to the SS pin and ground sets the start-up time to 0.6 ms.
15 PG
Power-Good Output. This open-drain output requires an external pull-up resistor. If the device is in shutdown
mode, current-limit mode, or thermal shutdown mode, or if VOUT falls below 90% of the nominal output
voltage, the PG pin immediately transitions low.
16 EN
Enable Input. Drive the EN pin high to turn on the regulator. Drive the EN pin low to turn off the regulator. For
automatic startup, connect the EN pin to the VIN pin.
EP Exposed Pad. The exposed pad is electrically connected to GND. It is recommended that this pad be connected
to a ground plane on the PCB. The exposed pad is on the bottom of the package.
Rev. 0 | Page 6 of 18

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