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PDF ADP1763 Data sheet ( Hoja de datos )
| Número de pieza | ADP1763 | |
| Descripción | CMOS Linear Regulator | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
3 A maximum output current
Low input voltage supply range
VIN = 1.10 V to 1.98 V, no external bias supply required
Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V
Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V
Ultralow noise: 2 μV rms, 100 Hz to 100 kHz
Noise spectral density
4 nV/√Hz at 10 kHz
3 nV/√Hz at 100 kHz
Low dropout voltage: 95 mV typical at 3 A load
Operating supply current: 4.5 mA typical at no load
±1.5% fixed output voltage accuracy over line, load, and
temperature
Excellent power supply rejection ratio (PSRR) performance
59 dB typical at 10 kHz at 3 A load
43 dB typical at 100 kHz at 3 A load
Excellent load/line transient response
Soft start to reduce inrush current
Optimized for small 10 μF ceramic capacitors
Current-limit and thermal overload protection
Power-good indicator
Precision enable
16-lead, 3 mm × 3 mm LFCSP package
APPLICATIONS
Regulation to noise sensitive applications such as radio
frequency (RF) transceivers, analog-to-digital converter
(ADC) and digital-to-analog converter (DAC) circuits,
phase-locked loops (PLLs), voltage controlled oscillators
(VCOs) and clocking integrated circuits
Field-programmable gate array (FPGA) and digital signal
processor (DSP) supplies
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP1763 is a low noise, low dropout (LDO) linear regulator. It
is designed to operate from a single input supply with an input
voltage as low as 1.10 V without the requirement of an external bias
supply to increase efficiency and provide up to 3 A of output current.
The low 95 mV typical dropout voltage at a 3 A load allows the
ADP1763 to operate with a small headroom while maintaining
regulation and providing better efficiency.
The ADP1763 is optimized for stable operation with small 10 μF
ceramic output capacitors. The ADP1763 delivers optimal
transient performance with minimal board area.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
3 A, Low VIN, Low Noise,
CMOS Linear Regulator
ADP1763
TYPICAL APPLICATION CIRCUITS
VIN = 1.8V
CIN
10µF
RPULL-UP
100kΩ
PG
ADP1763
VIN VOUT
SENSE
EN
PG
SS VADJ
VOUT = 1.5V
COUT
10µF
ON
OFF
CSS
10nF
CREG
1µF
VREG
REFCAP
GND
CREF
1µF
Figure 1. Fixed Output Operation
VIN = 1.8V
CIN
10µF
RPULL-UP
100kΩ
PG
ADP1763
VIN VOUT
SENSE
EN
PG
SS VADJ
CSS
10nF
CREG
1µF
VREG
REFCAP
GND
VOUT = 1.5V
COUT
10µF
ON
OFF
CREF
1µF
RADJ
10kΩ
Figure 2. Adjustable Output Operation
Table 1. Related Devices
Device
Input Maximum
Voltage Current
ADP1761 1.10 V to 1 A
1.98 V
ADP1762 1.10 V to 2 A
1.98 V
ADP1740/ 1.6 V to 2 A
ADP1741 3.6 V
ADP1752/ 1.6 V to 0.8 A
ADP1753 3.6 V
ADP1754/ 1.6 V to 1.2 A
ADP1755 3.6 V
Fixed/
Adjustable
Fixed/adjustable
Fixed/adjustable
Fixed/adjustable
Fixed/adjustable
Fixed/adjustable
Package
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
The ADP1763 is available in fixed output voltages ranging from
0.9 V to 1.5 V. The output of the adjustable output model can be
set from 0.5 V to 1.5 V through an external resistor connected
between VADJ and ground.
The ADP1763 has an externally programmable soft start time by
connecting a capacitor to the SS pin. Short-circuit and thermal
overload protection circuits prevent damage in adverse conditions.
The ADP1763 is available in a small 16-lead LFCSP package for the
smallest footprint solution to meet a variety of applications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADP1763
Data Sheet
Parameter
THERMAL SHUTDOWN
Threshold
Hysteresis
POWER-GOOD (PG) OUTPUT THRESHOLD
Output Voltage
Falling
Rising
PG OUTPUT
Output Voltage Low
Leakage Current
Delay1
PRECISION EN INPUT
Logic Input
High
Low
Input Logic Hysteresis
Input Leakage Current
Input Delay Time
UNDERVOLTAGE LOCKOUT
Input Voltage
Rising
Falling
Hysteresis
Symbol
TSSD
TSSD-HYS
Test Conditions/Comments
TJ rising
Min Typ Max Unit
150 °C
15 °C
PGFALL
PGRISE
PGLOW
IPG-LKG
PGDELAY
ENHIGH
ENLOW
ENHYS
IEN-LKG
tIEN-DLY
UVLO
UVLORISE
UVLOFALL
UVLOHYS
1.1 V ≤ VIN ≤ 1.98 V
1.1 V ≤ VIN ≤ 1.98 V
1.1 V ≤ VIN ≤ 1.98 V, IPG ≤ 1 mA
1.1 V ≤ VIN ≤ 1.98 V
ENRISING to PGRISING
1.1 V ≤ VIN ≤ 1.98 V
EN = VIN or GND
From EN rising from 0 V to VIN to 0.1 × VOUT
TJ = −40°C to +125°C
TJ = −40°C to +125°C
−7.5 %
−5 %
0.35
0.01 1
0.75
V
μA
ms
595 625 690 mV
550 580 630 mV
45 mV
0.01 1
μA
100 μs
1.01 1.06 V
0.87 0.93
V
80 mV
1 Guaranteed by design and characterization; not production tested.
2 Based on an endpoint calculation using 10 mA and 3 A loads.
3 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output
voltages above 1.1 V.
4 Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of its nominal value.
5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS
Table 3.
Parameter
CAPACITANCE1
Input
Output
Regulator
Reference
CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR)
CIN, COUT
CREG, CREF
Symbol
CIN
COUT
CREG
CREF
RESR
Test Conditions/Comments
TA = −40°C to +125°C
TA = −40°C to +125°C
Min Typ Max Unit
7.0 10
7.0 10
0.7 1
0.7 1
μF
μF
μF
μF
0.001
0.001
0.5 Ω
0.2 Ω
1 The minimum input and output capacitance must be >7.0 μF over the full range of the operating conditions. Consider the full range of the operating conditions in the
application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U
capacitors are not recommended for use with any LDO.
Rev. 0 | Page 4 of 18
5 Page 
ADP1763
–10
–20
–30
IIIILLLLOOOOAAAADDDD
=
=
=
=
500mA
1A
2A
3A
–40
–50
–60
–70
–80
–90
–100
–110
1
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency for
Various Input Voltages, VOUT = 1.3 V, VIN = 1.7 V
Data Sheet
Rev. 0 | Page 10 of 18
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ADP1763.PDF ] | |
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