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PDF PL123-09 Data sheet ( Hoja de datos )
| Número de pieza | PL123-09 | |
| Descripción | Low Skew Zero Delay Buffer | |
| Fabricantes | Micrel Semiconductor | |
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PL123-05/-09
FEATURES
Low Skew Zero Delay Buffer
DESCRIPTION
Frequency Range 10MHz to 134 MHz
Output Options:
o 5 outputs PL123-05
o 9 outputs PL123-09
Zero input - output delay
Optional Drive Strength:
Standard (8mA) PL123-05/-09
High (12mA) PL123-05H/-09H
3.3V, ±10% operation
Available in Commercial and Industrial temperature
ranges
Available in 16-Pin SOP or TSSOP (PL123-09),
and 8-Pin SOP (PL123-05) packages
The PL123-05/-09 (-05H/-09H for High Drive) are high
performance, low skew, low jitter zero delay buffers
designed to distribute high speed clocks. They have
one (PL123-05) or two (PL123-09) low-skew output
banks, of 4 outputs each, that are synchronized with
the input. The PL123-09 allows control of the banks of
outputs by using the S1 and S2 inputs as shown in the
Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
REF PLL
Mux
S1 Selector
Inputs
S2 (PL123-09 Only)
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
REF
CLKA2
CLKA1
GND
1
2
3
4
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
8 CLKOUT
7 CLKA4
6 VDD
5 CLKA3
16 CLKOUT
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13 Page 1
1 page  
PL123-05/-09
SWITCHING CHARACTERISTICS [5]
Parameter Name
Test Conditions
Low Skew Zero Delay Buffer
Min. Typ. Max. Unit
t1 Output Frequency
30-pF load
10-pF load
10 – 100 MHz
10 – 134 MHz
Duty Cycle [4] = t2 ÷ t1
Measured at 1.4V, FOUT = 66.67MHz
40 50 60 %
Duty Cycle [4] = t2 ÷ t1
Measured at 1.4V, FOUT <50MHz
45 50 55 %
Rise Time [4]
Measured between 0.8V and 2.0V
t3 Rise Time [4] (High Drive) Measured between 0.8V and 2.0V
– – 2.5 ns
– – 1.5 ns
Fall Time [4]
Measured between 0.8V and 2.0V
t4 Fall Time [4] (High Drive) Measured between 0.8V and 2.0V
– – 2.5 ns
– – 1.5 ns
t5
Output to Output Skew
All outputs equally loaded
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge [4]
Measured at VDD/2
– – 250 ps
– 0 ±350 ps
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL bypass
CLKOUT Rising Edge [4] mode, PL123-09 only.
1
5 8.5 ns
t7 Device to Device Skew [4] Measured at VDD/2 on the CLKOUT pin
– 0 700 ps
t8
Output Slew Rate [4]
Measured between 0.8V and 2.0V using Test
Circuit #2
1
– – V/ns
tJ Cycle to Cycle Jitter [4]
tLOCK PLL Lock Time [4]
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented on
REF pin
–
–
75 200 ps
– 1 ms
Notes:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5. All parameters are specified with loaded outputs.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13 Page 5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet PL123-09.PDF ] | |
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