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PL500-16 데이터시트 PDF




Micrel Semiconductor에서 제조한 전자 부품 PL500-16은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 PL500-16 자료 제공

부품번호 PL500-16 기능
기능 Low Phase Noise VCXO
제조업체 Micrel Semiconductor
로고 Micrel Semiconductor 로고


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PL500-16 데이터시트, 핀배열, 회로
FE AT UR E S
PL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
PIN CONFIGURATION
VCXO with Divider Selection (DIVSEL) input pin
PL500-15: ÷8, ÷16
PL500-16: ÷2, ÷4
VCXO output for the 1MHz to 18MHz range
16MHz to 36MHz fundamental crystal input.
Low phase noise (-130 dBc @ 10kHz offset
using a 35.328MHz crystal).
LVCMOS output with OE tri-state control.
Integrated high linearity variable capacitors.
12mA drive capability at TTL output.
± 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5V ~ 3.3V operation.
Available in 8-Pin SOP, 6-pin SOT23 GREEN/
RoHS compliant packages, or DIE.
DESCRIPTION
The PL500-15/16 is a low cost, high performance
and low phase noise VCXO for the 1MHz to 18MHz
range, providing less than -130dBc at 10kHz offset
when using a 35.328MHz crystal. The very low jitter
(2.5 ps RMS period jitter) makes this chip ideal for
applications requiring voltage controlled frequency
sources. Input crystal can range from 16MHz to
36MHz (fundamental resonant mode).
BLOCK DIAGRAM
XIN
VCON
DIVSEL^
GND
18
27
36
45
SOP-8L
XOUT
OE^
VDD
CLK
VCON
GND
XIN
1
2
3
6 CLK
5 VDD
4 XOUT
SOT23-6L*
^: Denotes internal Pull-up
*: SOT package offers single divider option only
DIVIDER SELECTION LOGIC LEVELS
Part #
DivSel State
Operation
PL500-15
1 (Default)*
0
PL500-16
1 (Default)*
0
* Setting for SOT23 package
÷16
÷8
÷4
÷2
DIVSEL
XIN
XOUT
VCON
Xtal
Osc
Varicap
Selectable
Divider
CLK
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 7/01/10 Page 1




PL500-16 pdf, 반도체, 판매, 대치품
PL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
4. Jitter and Phase Noise Specifications
PARAMETERS
CONDITIONS
MIN. TYP. MAX. UNITS
RMS Period Jitter
(1 sigma 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
With capacitive decoupling
between VDD and GND.
13.5MHz @100Hz offset
13.5MHz @1kHz offset
13.5MHz @10kHz offset
13.5MHz @100kHz offset
13.5MHz @1MHz offset
2.5 ps
-100 dBc/Hz
-125 dBc/Hz
-142 dBc/Hz
-150 dBc/Hz
-150 dBc/Hz
5. DC Specifications
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
Operating Voltage
Output Low Voltage at
CMOS level
Output High Voltage at
CMOS level
Output drive current
VCXO Control Voltage
SYMBOL
IDD
VDD
VOLC
VOHC
VCON
CONDITIONS
FXIN = 27MHz
Output load of
15pF
3.3V
2.5V
IOL = +4mA
IOH = -4mA
For VOL<0.4V or VOH>2.4V
MIN.
2.25
VDD 0.4
8
0
TYP.
3.7
2.4
9.5
MAX.
5
3.5
3.63
0.4
UNITS
mA
V
V
V
mA
VDD V
6. Crystal Specifications
PARAMETERS
SYMBOL MIN. TYP. MAX. UNITS
Crystal Loading Rating (VCON = 1.65V, 3.3V VDD)
Crystal Loading Rating (VCON = 1.25V, 2.5V VDD)
Maximum Sustainable Drive Level
Operating Drive Level
Max C0
CL (xtal)
(see note
below)
7.8
pF
8.9
200 W
50 W
5 pF
C0/C1
ESR
250 -
RS 30 Ω
Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
Note that the Cload values above are for the IC only, and do not include PCB parasitics. Crystal specifications for Cload include PC B parasitics.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 7/01/10 Page 4

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