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부품번호 CD22202 기능
기능 5V Low Power DTMF Receiver
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CD22202 데이터시트, 핀배열, 회로
November 2002
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CD22202,
CD22203
5V Low Power DTMF Receiver
Features
Description
• Central Office Quality
• No Front End Band Splitting Filters Required
• Single, Low Tolerance, 5V Supply
• Detects Either 12 or 16 Standard DTMF Digits
• Uses Inexpensive 3.579545MHz Crystal for Reference
• Excellent Speech Immunity
• Output in Either 4-Bit Hexadecimal Code or Binary
Coded 2-of-8
• Synchronous or Handshake Interface
• Three-State Outputs
• Excellent Latch-Up Immunity
Part Number Information
PART
NUMBER
CD22202E
CD22203E
TEMP.
RANGE (oC) PACKAGE
0 to 70 18 Ld PDIP
0 to 70 18 Ld PDIP
PKG. NO.
E18.3
E18.3
The CD22202 and CD22203 complete dual-tone multiple
frequency (DTMF) receivers detect a selectable group of 12
or 16 standard digits. No front-end pre-filtering is needed.
The only externally required components are an inexpensive
3.579545MHz TV “colorburst’’ crystal (for frequency refer-
ence) and a bias resistor. Extremely high system density is
possible through the use of the clock output of a crystal con-
nected CD22202/CD22203 receiver to drive the time bases
of additional receivers. This is a monolithic integrated circuit
fabricated with low-power, complementary symmetry CMOS
processing. It only requires a single low tolerance power
supply.
The CD22202 and CD22203 employ state-of-the-art circuit
technology to combine the digital and analog functions on
the same CMOS chip using a standard digital semiconductor
process. The analog input is preprocessed by 60Hz reject
and band splitting filters and then hard limited to provide
AGC. Eight Bandpass filters detect the individual tones. The
digital post processor times the tone durations and provides
the correctly coded digital outputs. Outputs interface directly
to standard CMOS circuitry and are three-state enabled to
facilitate bus oriented architectures.
Pinout
CD22202, CD22203
(PDIP)
TOP VIEW
D1 1
HEX/B28 2
EN 3
IN1633 4
VDD
ED (203 ONLY),
NC (202)
VSS
5
6
7
XEN 8
ANALOG IN 9
18 D2
17 D4
16 D8
15 CLRDV
14 DV
13 ATB
12 XIN
11 XOUT
10 VSS
Functional Diagram
9
ANALOG IN
13
ATB
8
XEN
XIN
12
11
XOUT
LOW B/P
FILTERS
HIGH B/P
FILTERS
CHIP
CLOCKS
VOLTAGE
REG./REF.
5
VDD
10 7
VSS
6 ED-203
NC-202
15
CLRDV
14
DV
2
HEX/B28
1
D1
18
D2
17
D4
16
D8
3
EN
4
INI633
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
FN1695.4




CD22202 pdf, 반도체, 판매, 대치품
CD22202, CD22203
3.579545MHz
1M
XIN
XOUT
VDD
12 11
ATB
13
CD22202/22203
8
XEN
sensed and decoded at the output pins D1, D2, D4, and D8.
DV remains high until a valid pause occurs or CLRDV is
raised high, whichever is sooner. This handshake can save
microprocessor time.
DTMF Dialing Matrix
COL 0
1209Hz
COL 1
1336Hz
COL 2
1477Hz
COL 3
1633Hz
XIN CONNECTED TO VDD
12
13 CD22202/22203
XEN
8
ROW 0
697Hz
1
2
3
A
ROW 1
770Hz
4
5
6
B
ROW 2
852Hz
7
8
9
C
UP TO 10 DEVICES
ROW 3
941Hz
*
0
#
D
HEX/B28
FIGURE 2. CRYSTAL OSCILLATOR
NOTE: Column 3 is for special applications and is not normally used
in telephone dialing.
This pin selects the format of the digital output code. When
HEX/B28 is tied high, the output is hexadecimal. When tied
low, the output is binary coded 2-of-8. The following table
describes the two output codes.
TABLE 1. OUTPUT CODES
DIGIT
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
HEXADECIMAL
D8 D4 D2 D1
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
BINARY CODED 2-OF-8
D8 D4 D2 D1
0000
0001
0010
0100
0101
0110
1000
1001
1010
1101
1100
1110
0011
0111
1011
1111
IN1633
When tied high, this pin inhibits detection of tone pairs con-
taining the 1633Hz component. For detection of all 16 stan-
dard digits, IN1633 must be tied low.
N/C Pin
This pin has no internal connection and should be left floating.
Digital Inputs and Outputs
All digital inputs and outputs of the DTMF receivers are rep-
resented by the schematic below. Only the “analog in” pin is
different, and is described above. Care must be exercised
not to exceed the voltage or current ratings on these pins as
listed in the “maximum ratings” section.
VDD
DIGITAL
INPUT
CMOS
DIGITAL
CIRCUITRY
DIGITAL
OUTPUT
VSS
FIGURE 3. DIGITAL INPUTS AND OUTPUTS
ED
This pin, on the CD22203 only, indicates the presence of fre-
quencies which are likely to be DTMF digits, but have not yet
been verified by a DV signal. It is comparable to a “button-
down” output, and it is useful as an EARLY DETECT signal to
interrupt a microprocessor for digit storage and validation.
DV and CLRDV
DV signals a detection by going high after a valid tone pair is
Input Filter
The CD22202 and CD22203 will tolerate total input noise of
a maximum of 12dB below the lowest amplitude tone. For
most telephone applications, the combination of the high
frequency attenuation of the telephone line and internal
band limiting make special circuitry at the input to these
receivers unnecessary. However, noise near the 56kHz
internal sampling frequency will be aliased (folded back)
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