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CD22402 데이터시트 PDF




Intersil Corporation에서 제조한 전자 부품 CD22402은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 CD22402 기능
기능 Sync Generator for TV Applications and Video Processing Systems
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CD22402 데이터시트, 핀배열, 회로
May 1999
Semiconductor
CD22402NO
Call
CRoeErnOCetrOBmaSMlaOAiMl:pLEpEcNlTeiDcnEaEtaPtDipoRpRnO@sEDP1hUL-aC8Ar0rTCi0sE-.4cM4o2Em-N7T74S7yncanGdenVeidraetoorPfroorceTsVsAinpgpSlicyasttieomnss
[ /Title
(CD2240
2)
/Subject
(Sync
Genera-
tor for
TV
Applica-
tions and
Video
Process-
Features
• Interlaced Composite Sync Output
• Automatic Genlock Capability
• Crystal Oscillator Operation
• 525 or 625 Line Operation
• Vertical Reset Option
• Wide Power Supply Operating Voltage . . . . . 4V to 15V
Applications
• Cameras
• Monitors and Displays
• CATV
• Teletext
• Video Games
• Sync Restorer
• Video Service Instruments
Part Number Information
PART NUMBER
CD22402D
CD22402E
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 24 Ld SBDIP
-40 to 85 24 Ld PDIP
PKG.
NO.
D24.6
E24.6
Description
The Harris CD22402 (Note) is a CMOS LSI sync generator that
produces all the timing signals required to drive a fully 2-to-1
interlaced 525-line 30-frame/second, or 625-line 25-frame/sec-
ond TV camera or video processing system. A complete sync
waveform is produced which begins each field with six serrated
vertical sync pulses, preceded and followed by six half-width
double frequency equalizing pulses. The sync output is gated by
the master clock to preserve horizontal phase continuity during
the vertical interval.
The CD22402 can be operated either in “genlock” mode, in
which it is synchronized with a reference sync pulse train from
another TV camera, or in “stand-alone” mode, in which it is syn-
chronized with a local on-chip crystal oscillator (the crystal and
two passive components are off chip). Also, the circuit can
sense the presence or absence of a reference sync pulse train
and automatically select the “genlock” or “stand-alone” mode.
A frame sync pulse is produced at the beginning of every odd
field. The vertical counter can be reset to either the first equalizing
pulse or the first vertical sync pulse of the vertical interval. The
interlaced sync provided by the CD22402 differs from RS-170 by
having slightly narrower sync and equalizing pulses. The clock
frequency of 32 times horizontal rate allows for approximately 4µs
horizontal pulse widths and 2µs equalizing pulses. Otherwise
operation can be phase locked to a color sub-carrier for a full
interlaced operating system.
The CD22402 is operable with a single supply over a voltage
range of 4V to 15V.
Pinout
CD22402 (PDIP, SBDIP)
TOP VIEW
DELAY, GENLOCK TO CRYSTAL OSCILLATOR 1
CRYSTAL OSCILLATOR FEEDBACK TAP 2
VSS 3
HORIZONTAL DRIVE OUTPUT 4
MIXED SYNC OUTPUT 5
GENLOCK OSCILLATOR CAPACITOR CONNECTION 6
MIXED BEAM BLANKING OUTPUT 7
VERTICAL COUNTER RESET TO FIRST EQUALIZING PULSE 8
VERTICAL DRIVE OUTPUT 9
VERTICAL RESET TO FIRST VERTICAL SYNC PULSE 10
HORIZONTAL CLAMP OUTPUT 11
VSS 12
24 RESISTOR CONNECTION FOR GENLOCK OSCILLATOR
23 MASTER FREQUENCY INPUT
22 R-C CONNECTION FOR GENLOCK OSCILLATOR
21 DELAY, GENLOCK TO CRYSTAL OSCILLATOR
20 GENLOCK INPUT (COMPOSITE SYNC)
19 VDD
18 525 LINE TO 625 LINE OPERATION SWITCH
17 VERTICAL PROCESSING BLANKING OUTPUT
16 SHORT VERTICAL DRIVE OUTPUT
15 FRAME SYNC OUTPUT (ODD FIELD)
14 HORIZONTAL PROCESSING BLANKING OUTPUT
13 MIXED PROCESSING BLANKING OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
8-40
File Number 1686.5




CD22402 pdf, 반도체, 판매, 대치품
CD22402
Absolute Maximum Ratings
DC Supply Voltage (Referenced to VSS Terminal) . . . . . . . . . . . 15V
Input Voltage Range, All Inputs (Notes 2, 3) . . . . . . VSS VI VDD
DC Input Current, Any One Input (Note 2) . . . . . . . . . . . . . . ±10mA
Operating Conditions
Temperature Range
CD22402D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CD22402E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
50
10
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
Maximum Junction Temperature (SBDIP Package) . . . . . . . . 175oC
Maximum Junction Temperature (PDIP Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS. Input currents must
not exceed 10mA even when the power is off.
3. A connection must be provided at every input terminal. All unused inputs must be connected to VDD or VSS, whichever is appropriate.
Electrical Specifications Values at -55oC, 25oC, 125oC Apply to D Package
Values at -40oC, 25oC, 85oC Apply to E Package
TEST
CONDITIONS
PARAMETER
VO VDD
SYMBOL (V)
(V) -55oC -40oC 85oC 125oC
DC ELECTRICAL SPECIFICATIONS
Quiescent Device Current
IDD (Max)
-
5
-
-
-
-
- 10 - - - -
- 15 - - - -
Output Low (Sink) Current
IOL (Min)
0.5
5
5 100 96 66 56
5 1200 1155 787 672
0.5 10 248 239 164 140
10 10 3000 2868 1968 1680
Output High (Source) Cur-
rent
IOH (Min)
4.5
0
5 -100 -96 -66 -56
5 -1200 -1155 -787 -672
9.5 10 -248 -239 -164 -140
0 10 -3000 -2868 -1968 -1680
Output Voltage Low Level VOL (Max)
-
-
5 0.15 0.15 0.15 0.15
10 0.15 0.15 0.15 0.15
Output Voltage High Level VOH (Min)
-
-
5 4.85 4.85 4.85 4.85
10 9.85 9.85 9.85 9.85
Input Low Voltage
VIL (Max) 0.5, 4.5 5 1.5 1.5 1.4 1.4
1, 9 10
3
3 2.9 2.9
Input High Voltage
VIH (Min) 0.5, 4.5 5 3.6 3.6 3.5 3.5
1, 9 10 7.1
7.1
7
7
Input Current
IIN (Max)
-
-
-
-
-
-
Refer to the CD4000B Series data book 250.5 for general operating and application considerations.
25oC
MIN TYP
0.5 0.75
1.5 2
34
80 160
960 1920
200 400
2400 4800
-80 -160
-960 -1920
-200 -400
-2400 -4800
--
--
4.85 -
9.85 -
- 2.25
- 4.5
3.5 2.25
7 4.5
- 10
MAX
1
2.5
5
-
-
-
-
-
-
-
-
0.15
0.15
-
-
1.5
3
-
-
-
UNITS
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
pA
8-43

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CD22402 전자부품, 판매, 대치품
CD22402
Timing Waveforms (Continued)
MICROSECONDS
500kHz
OSC. PIN 2 OR 6
MIXED BLANKING
PIN 13
0
HORIZ. DRIVE PIN 4
CATHODE
BLANKING
PIN 7
2
HORIZ. CLAMP
PIN 11
H. SYNC
MIXED SYNC
PIN 5
EQUALIZING
PULSE
V. SYNC
4 6 8 10 12
12µs
4µs
8µs
2µs
4µs
2µs
26µs
28 32
2µs
4µs
FIGURE 4. SYNC GENERATOR TIMING - 625/50Hz, HORIZONTAL TIMING WAVEFORMS
VERTICAL RESET TO
FIRST EQUALIZING
PULSE
LINE NO
MIXED SYNC
PIN 5
0
VERT. DRIVE
PIN 9
VERTICAL
PROCESSING
BLANKING
PIN 17
WIDE BLANKING
PIN 13
SHORT VERTICAL
DRIVE PIN 16
CATHODE
BLANKING
PIN 7
FRAME SYNC
PIN 15
(ON ALTERNATE FIELDS)
VERTICAL RESET
TO FIRST
VERTICAL PULSE
1 2 34 5 6
78
0.57ms
1.36ms
0.194ms
2µs (NOT TO SCALE)
9 10
21
FIGURE 5. SYNC GENERATOR TIMING - 625/50Hz, VERTICAL TIMING WAVEFORMS
8-46

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Intersil Corporation
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