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AUIRL7736M2TR 데이터시트 PDF




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AUIRL7736M2TR 데이터시트, 핀배열, 회로
 
AUTOMOTIVE GRADE
AUIRL7736M2TR
Logic Level
Advanced Process Technology
Optimized for Automotive Motor Drive, DC-DC and
other Heavy Load Applications
Exceptionally Small Footprint and Low Profile
High Power Density
Low Parasitic Parameters
Dual Sided Cooling
175°C Operating Temperature
Repetitive Avalanche Capability for Robustness and Reliability
Lead free, RoHS and Halogen free
 Automotive Qualified *
Automotive DirectFET® Power MOSFET
V(BR)DSS
RDS(on) typ.
max.
ID (Silicon Limited)
Qg (typical)
40V
2.2m
3.0m
112A
52nC
  
SS
D
G
SS
D
Applicable DirectFET® Outline and Substrate Outline
M4 DirectFET® ISOMETRIC
SB SC
M2 M4
L4 L6 L8
Description
The AUIRL7736M2 combines the latest Automotive HEXFET® Power MOSFET Silicon technology with the advanced DirectFET® packaging
technology to achieve exceptional performance in a package that has the footprint of an SO-8 or 5X6mm PQFN and only 0.7mm profile. The
DirectFET® package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or
convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET®
package allows dual sided cooling to maximize thermal transfer in automotive power systems.
his HEXFET® Power MOSFET is designed for applications where efficiency and power density are of value. The advanced DirectFET® packaging
platform coupled with the latest silicon technology allows the AUIRL7736M2 to offer substantial system level savings and performance improvement
specifically in high frequency DC-DC, motor drive and other heavy load applications on ICE, HEV and EV platforms. The AUIRL7736M2 can be utilized
together with the AUIRL7732S2 as a sync/control MOSFET pair in a buck converter topology. This MOSFET utilizes the latest processing techniques
to achieve low on-resistance and low Qg per silicon area. Additional features of this MOSFET are 175°C operating junction temperature and high
repetitive peak current capability. These features combine to make this MOSFET a highly efficient, robust and reliable device for high current
automotive applications.
Base Part Number  
Package Type  
Standard Pack
Form
Quantity
Orderable Part Number  
AUIRL7736M2
DirectFET Medium Can
Tape and Reel
4800
AUIRL7736M2TR
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; and
functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under
board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified.
Parameter
Max.
Units
VDS
VGS
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
ID @ TA= 25°C
IDM
PD @TC = 25°C
PD @TA = 25°C
EAS
EAS (Tested)
IAR
EAR
TP
TJ
TSTG
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Pulsed Drain Current
Power Dissipation
Power Dissipation
Single Pulse Avalanche Energy (Thermally Limited)
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Soldering Temperature
Operating Junction and
Storage Temperature Range
40
±16
112
79
179
22
450
63
2.5
68
119
See Fig. 16, 17, 18a, 18b
260
-55 to + 175
V
A
W
mJ
A
mJ
°C  
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at www.infineon.com
1 2015-10-29




AUIRL7736M2TR pdf, 반도체, 판매, 대치품
 
1000
100
10
TOP
BOTTOM
VGS
10V
8.0V
6.0V
4.5V
3.5V
3.0V
2.8V
2.5V
1
0.1
0.1
2.5V
60µs PULSE WIDTH
Tj = 25°C
1 10 100
VDS, Drain-to-Source Voltage (V)
1000
Fig. 1 Typical Output Characteristics
7
ID = 67A
6
5
4
TJ = 125°C
3
2
TJ = 25°C
1
0 2 4 6 8 10 12 14 16 18
VGS, Gate -to -Source Voltage (V)
Fig. 3 Typical On-Resistance vs. Gate Voltage
1000
TJ = -40°C
100 TJ = 25°C
TJ = 175°C
10
1
0.1
1
VDS = 25V
60µs PULSE WIDTH
2345
VGS, Gate-to-Source Voltage (V)
Fig 5. Transfer Characteristics
4
1000
100
AUIRL7736M2TR
TOP
BOTTOM
VGS
10V
8.0V
6.0V
4.5V
3.5V
3.0V
2.8V
2.5V
2.5V
10
1
0.1
60µs PULSE WIDTH
Tj = 175°C
1 10 100
VDS, Drain-to-Source Voltage (V)
1000
Fig. 2 Typical Output Characteristics
5
4
TJ = 125°C
3
2
TJ = 25°C
1
Vgs = 10V
0
0 25 50 75 100 125 150 175 200
ID, Drain Current (A)
Fig. 4 Typical On-Resistance vs. Drain Current
2.0
ID = 67A
VGS = 10V
1.5
1.0
0.5
-60 -40 -20 0 20 40 60 80 100 120 140160 180
TJ , Junction Temperature (°C)
Fig 6. Normalized On-Resistance vs. Temperature
2015-10-29

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AUIRL7736M2TR 전자부품, 판매, 대치품
  AUIRL7736M2TR
50
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
40 ID = 67A
30
20
10
0
25 50 75 100 125 150 175
Notes on Repetitive Avalanche Curves , Figures 16, 17:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 18a, 18b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 16, 17).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 15)
Starting TJ , Junction Temperature (°C)
Fig 17. Maximum Avalanche Energy vs. Temperature
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 18a. Unclamped Inductive Test Circuit
Fig 18b. Unclamped Inductive Waveforms
VDD 
Fig 19a. Gate Charge Test Circuit
Fig 19b. Gate Charge Waveform
Fig 20a. Switching Time Test Circuit
7
Fig 20b. Switching Time Waveforms
2015-10-29

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