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W255 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 W255은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 W255 자료 제공

부품번호 W255 기능
기능 200-MHz 24-Output Buffer
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


W255 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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W255 데이터시트, 핀배열, 회로
W255
200-MHz 24-Output Buffer for 4 DDR
or 3 SDRAM DIMMS
Features
Functional Description
• One input to 24-output buffer/driver
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS
• One additional output for feedback
• SMBus interface for individual output control
• Low skew outputs (< 100 ps)
• Supports 266-, 333-, and 400-MHz DDR SDRAM
• Dedicated pin for power management support
• Space-saving 48-pin SSOP package
The W255 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 24 outputs.
Designers can configure these outputs to support four unbuf-
fered DDR DIMMS or to support three unbuffered standard
SDRAM DIMMs and two DDR DIMMS. The W255 can be used
in conjunction with the W250 or similar clock synthesizer for
the VIA Pro 266 chipset.
The W255 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull up).
Block Diagram
BUF_IN
SDATA
SCLOCK
SMBus
Decoding
PWR_DWN#
SEL_DDR
Power Down Control
Pin Configuration[1]
FBOUT
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
FBOUT
VDD3.3_2.5
GND
DDR2T_SDRAM2 DDR0T_SDRAM10
DDR2C_SDRAM3 DDR0C_SDRAM11
DDR3T_SDRAM4 DRR1T_SDRAM0
DDR3C_SDRAM5 DDR1C_SDRAM1
DDR4T_SDRAM6
VDD3.3_2.5
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
GND
DDR2T_SDRAM2
DDR2C_SDRAM3
VDD3.3_2.5
DDR6T
BUF_IN
DDR6C
GND
DDR7T
DDR7C
DDR8T
DDR8C
DDR3T_SDRAM4
DDR3C_SDRAM5
VDD3.3_2.5
GND
DDR4T_SDRAM6
DDR9T
DDR4C_SDRAM7
DDR9C
DDR10T
DDR5T_SDRAM8
DDR5C_SDRAM9
VDD3.3_2.5
DDR10C
SDATA
SSOP
Top View
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
SEL_DDR*
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PWR_DWN#*
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
DDR11T
DDR11C
Note:
1. Internal 100K pull-up resistors present on inputs marked
with *. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07255 Rev. *D
Revised April 28, 2005




W255 pdf, 반도체, 판매, 대치품
W255
Maximum Ratings
Supply Voltage to Ground Potential ..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN) ............ –0.5V to VDD+0.5
Operating Conditions[2]
Storage Temperature .................................. –65°C to +150°C
Static Discharge Voltage........................................... > 2000V
(per MIL-STD-883, Method 3015)
Parameter
VDD3.3
VDD2.5
TA
COUT
CIN
Description
Supply Voltage
Supply Voltage
Operating Temperature (Ambient Temperature)
Output Capacitance
Input Capacitance
Min. Typ. Max. Unit
3.135
3.465
V
2.375
2.625
V
0 70 °C
6 pF
5 pF
Electrical Characteristics Over the Operating Range
Parameter
VIL
VIH
IIL
IIH
IOH
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output HIGH Current
IOL
VOL
VOH
IDD
IDD
IDDS
VOUT
Output LOW Current
Output LOW Voltage[3]
Output HIGH Voltage[3]
Supply Current[3]
(DDR-only mode)
Supply Current
(DDR-only mode)
Supply Current
Output Voltage Swing
VOC Output Crossing Voltage
INDC
Input Clock Duty Cycle
Test Conditions
For all pins except SMBus
VIN = 0V
VIN = VDD
VDD = 2.375V
VOUT = 1V
VDD = 2.375V
VOUT = 1.2V
IOL = 12 mA, VDD = 2.375V
IOH = –12 mA, VDD = 2.375V
Unloaded outputs, 133 MHz
Min.
2.0
–18
26
1.7
Loaded outputs, 133 MHz
PWR_DWN# = 0
See test circuity (refer to
Figure 1)
0.7
(VDD/2) –
0.1
48
Typ.
–32
35
VDD/2
Max.
0.8
50
50
0.6
400
500
100
VDD +0.6
(VDD/2) +
0.1
52
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
µA
V
V
%
Switching Characteristics [4]
Parameter
Name
Test Conditions
Min. Typ. Max.
– Operating Frequency
66
– Duty Cycle[3, 5] = t2 ÷ t1 Measured at 1.4V for 3.3V outputs INDC
Measured at VDD/2 for 2.5V outputs
5%
t3
SDRAM Rising Edge Rate[3]
Measured between 0.4V and 2.4V
1.0
t4
SDRAM Falling Edge Rate[3]
Measured between 2.4V and 0.4V
1.0
t3d
DDR Rising Edge Rate[3]
Measured between 20% to 80% of
0.5
output (refer to Figure 1)
200
INDC +
5%
2.75
2.75
1.50
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Unit
MHz
%
V/ns
V/ns
V/ns
Document #: 38-07255 Rev. *D
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W255 전자부품, 판매, 대치품
Layout Example for DDR 2.5V Only
+2.5V Supply
FB
VDDQ2
0.005 mF
C4
10 mF C3
GG
1G
2G V
3G
4
5
6
7G
8G V
9G
10
11 G
G 12 V
13 G
14
15
16 G
G 17 V
18 G
19
20
21
22 G
G 23 V
24 G
48
V 47
G 46
45
44
43
G 42
V 41
G 40
39
G 38
V 37
G 36
G 35
34
G 33
V 32
G 31
30
G 29
28
27
G 26
25
G
G
G
G
FB = Dale ILB1206 - 300 (300@ 100 MHz) or TDK ACB 2012L-120
Ceramic Caps C3 = 10–22 µF
C4 = 0.005 µF
G = VIA to GND plane layer V = VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
All bypass caps = 0.1 µF ceramic
W255
Document #: 38-07255 Rev. *D
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