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S6E2DH5GJA 데이터시트, 핀배열, 회로
S6E2DH Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Devices in the S6E2DH Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series
is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as
graphics engine, display controller, motor control timers, ADCs, and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
The products that are described in this data sheet are TYPE4-M4 category products. See the FM4 Family Peripheral Manual Main
Part (002-04856).
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 160 MHz frequency operation
Built-in FPU
Supports DSP instructions
Memory Protection Unit (MPU): improves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit system timer (Sys Tick): System timer for OS task
management
On-Chip Memories
Flash memory
This series has on-chip flash memory with these features:
384 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
Security function for code protection
Notes:
The read access to flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an
equivalent access to flash memory can be obtained by
Flash Accelerator System.
SRAM
This is composed of two independent SRAMs (SRAM0 and
SRAM2). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M4F core. SRAM2 is connected to the system bus of
Cortex-M4F core.
SRAM0: 32 Kbytes
SRAM2: 4 Kbytes
VRAM
This series is equipped with a SRAM for GDC.
Max 512 Kbytes
VFLASH
S6E2DH5GJA is equipped with a Flash for GDC.
2 Mbytes
External Bus Interface
Supports SRAM, NOR, NAND Flash and SDRAM devices
Up to two chip selects CS0 and CS8 (CS8 is only for
SDRAM)
8-/16-bit data width
Up to 25-bit address bit
Maximum area size : Up to 256 Mbytes
Supports address/data multiplexing
Supports external RDY function
Supports the scramble function
Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0x7FFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key.
Note: It is necessary to prepare the dedicated software
library to use the scramble function.
USB Interface (One channel)
A USB interface is composed of device and host.
USB device
USB2.0 Full-Speed supported
Max 6 EndPoint supported
EndPoint 0 is for control transfer
EndPoint 1, 2 can be selected for bulk-transfer,
interrupt-transfer or isochronous-transfer
EndPoint 3 to 5 can select bulk-transfer or
interrupt-transfer
EndPoint 1 to 5 comprise the double buffer
The size of each endpoint is as follows.
Endpoint 0, 2 to 5: 64 bytes
EndPoint 1: 256 bytes
USB host
USB2.0 Full-Speed / Low-Speed supported
Bulk-transfer, interrupt-transfer and isochronous-transfer
support
USB device connected/disconnected automatically detect
In/out token handshake packet automatically accepted
Max 256-byte packet-length supported
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-05038 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised March 4, 2016




S6E2DH5GJA pdf, 반도체, 판매, 대치품
S6E2DH Series
I2S Interface (TX x two channels, RX x two channels)
Support three transfer protocols
I2S
Left Justified
DSP mode
Master/Slave Mode selectable
RX only, TX only or TX and RX simultaneous operation
selectable
Word length is programmable from 7 bits to 32 bits
RX/TX FIFO integrated (RX: 66 words x 32 bits, TX: 66
words x 32 bits)
DMA, interrupts, or polling based data transfer supported
GDC Unit
Controller for external graphics display
Accelerator for 2D block image transfer (blit) operations
Embedded SRAM video memory
High-Speed Quad SPI (Serial Peripheral Interface for
external memory extensions)
SDRAM interface for external memory extensions
HBI (Hyper Bus Interface) interface for external memory
extensions
Maximum core system clock frequency : 160 MHz
Clock and Reset
Clocks
Five clock sources (two external oscillators, two internal CR
oscillator, and Main PLL) that are dynamically selectable.
Main clock:
Sub Clock :
High-speed internal CR Clock:
Low-speed internal CR Clock:
Main PLL Clock
4 MHz to 20 MHz
32.768 kHz
4 MHz
100 kHz
Resets
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes are supported.
Sleep
Timer
RTC
Stop
Deep standby RTC (selectable from with/without RAM
retention)
Deep standby Stop (selectable from with/without RAM
retention)
Peripheral Clock Gating
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral functions
not used.
VBAT
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
RTC
32 kHz oscillation circuit
Power-on circuit
Back up register : 32 bytes
Port circuit
Debug
Serial Wire Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Two Power Supplies
Power supply:
VCC= 2.7 V to 3.6 V (when USB or GDC unit is not used)
= 3.0 V to 3.6 V (when USB or GDC unit is used)
Power supply for VBAT:
VBAT = 1.65 V to 3.6 V
Document Number: 002-05038 Rev.*A
Page 4 of 183

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S6E2DH5GJA 전자부품, 판매, 대치품
S6E2DH Series
1. Product Lineup
Memory Size
Product Name
On-chip Flash memory
On-chip SRAM
VRAM for GDC
VFLASH for GDC
SRAM
SRAM0
SRAM2
Function
Pin count
Product Name
CPU
Power supply voltage range
USB2.0 (Device/Host)
CAN-FD (non-ISO CAN FD)
DMAC
DSTC
GraphicsDisplay controller
GDC High-Speed Quad SPI
unit Hyper Bus Interface
SDRAM-IF
Freq.
External Bus Interface
Multi-function Serial Interface (UART/CSIO/LIN/I2C)
Base Timer (PWC/Reload timer/PWM/PPG)
A/D activation compare
6ch.
Input capture
4ch.
Free-run timer
3ch.
Output compare
6ch.
Waveform generator
3ch.
PPG
3ch.
SD Card Interface
I2S
QPRC
Dual Timer
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog Timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
Built-in CR
High-speed
Low-speed
Debug Function
Unique ID
S6E2DH5G0A
S6E2DH5J0A
-
384 Kbytes
36 Kbytes
32 Kbytes
4 Kbytes
512 Kbytes
S6E2DH5GJA
2 Mbytes
S6E2DH5G0A
S6E2DH5J0A
S6E2DH5GJA
120/161
176
120
Cortex-M4F, MPU, NVIC 128ch.
160 MHz
2.7 V to 3.6 V
1ch.
1ch.
8ch.
128ch.
1 unit
1ch. (VFLASH only)
1 unit
-
- 1ch. -
Addr:25-bit (Max), Data: 8-/16-bit, CS:2 (Max)
SRAM, NOR Flash, NAND Flash, SDRAM
8ch. (Max)
8ch. (Max)
1 unit
98 pins (Max)
1 unit
2 units
1ch.
1 unit
1 unit
1 unit
Yes(Fixed, Programmable)
1ch. (SW) + 1ch. (HW)
16 pins (Max)+ NMI × 1
154 pins (Max)
24ch. (2 units)
Yes
2ch.
4 MHz
100 kHz
SWJ-DP/ETM
Yes
90 pins (Max)
Document Number: 002-05038 Rev.*A
Page 7 of 183

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