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S6E2CC8JFA 데이터시트, 핀배열, 회로
S6E2CC Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Devices in the S6E2CC Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This
series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as
motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I2C, LIN). The products that
are described in this data sheet are placed into TYPE3-M4 product categories "FM4 Family Peripheral Manual Main Part
(002-04856)."
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 200 MHz frequency operation
FPU built-in
Support DSP instructions
Memory protection unit (MPU): improves the reliability of an
embedded system
Integrated nested vectored interrupt controller (NVIC): 1 NMI
(non-maskable interrupt) and 128 peripheral interrupts and
16 priority levels
24-bit system timer (Sys Tick): system timer for OS task
management
External Bus Interface
Supports SRAM, NOR, NAND flash and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-/32-bit data width
Up to 25-bit address bus
Supports address/data multiplexing
Supports external RDY function
Supports scramble function
Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0xDFFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key
Note: It is necessary to use the Cypress provided software
library to use the scramble function.
On-chip Memories
Flash memory
This series is based on two independent on-chip flash
memories.
Up to 2048 Kbytes
Built-in flash accelerator system with 16 Kbytes trace buffer
memory
Read access to flash memory that can be achieved without
wait-cycle up to an operating frequency of 72 MHz. Even at
the operating frequency more than 72 MHz, an equivalent
single cycle access to flash memory can be obtained by
the flash accelerator system.
Security function for code protection
SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to the I-code bus
and D-code bus of Cortex-M4F core. SRAM1 and SRAM2
are connected to system bus of Cortex-M4F core.
SRAM0: up to 192 Kbytes
SRAM1: 32 Kbytes
SRAM2: 32 Kbytes
USB Interface (Max two channels)
The USB interface is composed of a function and a host.
USB function
USB 2.0 Full-speed supported
Max 6 EndPoint supported
EndPoint 0 is control transfer
EndPoint 1, 2 can be selected bulk-transfer,
interrupt-transfer or isochronous-transfer
EndPoint 3 to 5 can select bulk-transfer or
interrupt-transfer
EndPoint 1 to 5 comprise double buffer
The size of each endpoint is as follows.
Endpoint 0, 2 to 5: 64 byte
EndPoint 1: 256 byte
USB host
USB2.0 Full-Speed/Low-Speed supported
Bulk-transfer, interrupt-transfer, and isochronous-transfer
support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet length supported
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-04980 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised February 5, 2016




S6E2CC8JFA pdf, 반도체, 판매, 대치품
S6E2CC Series
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs: a "hardware"
watchdog and a "software" watchdog.
The hardware watchdog timer is clocked by low-speed
internal CR oscillator. The hardware watchdog is thus active
in any power saving mode except RTC mode and Stop mode.
Cyclic Redundancy Check (CRC) Accelerator
The CRC accelerator helps to verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 generator polynomial: 0x1021
IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
Programmable Cyclic Redundancy Check
(PRGCRC) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16, IEEE-802.3 CRC32 and generating
polynomial are supported.
CCITT CRC16 generator polynomial: 0x1021
IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
Generating polynomial
SD Card Interface
It is possible to use the SD card that conforms to the
following standards.
Part 1 Physical Layer Specification version 3.01
Part E1 SDIO Specification version 3.00
Part A2 SD Host Controller Standard Specification version
3.00
1-bit or 4-bit data bus
Ethernet-MAC
Compliant with IEEE802.3 specification
10 Mbps/100 Mbps data transfer rates supported
MII/RMII for external PHY device supported.
MII: Max one channel
RMII: Max one channel
Full-duplex and half-duplex mode supported.
Wake-ON-LAN supported
Built-in dedicated descriptor-system DMAC
Built-in 2 Kbytes transmit FIFO and 2 Kbytes receive FIFO.
Compliant IEEE1558-2008 (PTP)
I2S (Inter-IC Sound Bus) Interface (TX x one
channel, RX x one channel)
Supports three transfer protocols
I2S
Left justified
DSP mode
Separate clock generation block for flexible system
integration options
Master/slave mode selectable
RX Only, TX Only or TX and RX simultaneous operation
selectable
Word length is programmable from 7-bits to 32-bits
RX/TX FIFO integrated (RX: 66 words x 32-bits, TX: 66
words x 32-bits)
DMA, interrupts, or polling based data transfer supported
High-speed Quad SPI
Up to 66 MHz clock rates for very fast data transfers to and
from SPI compatible devices.
Up to 256 Mbytes of memory mapped address space.
Single data rate (SDR)
Supports single, dual, and quad data modes
Built-in direct mode and command sequencer mode
Direct mode: Access by use of transmission
FIFO/reception FIFO (up to16 word x 32 bit)
Command sequencer mode: Automatic access assigned to
external device area.
Document Number: 002-04980 Rev.*A
Page 4 of 207

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S6E2CC8JFA 전자부품, 판매, 대치품
S6E2CC Series
Table of Contents
Features................................................................................................................................................................................... 1
1. Product Lineup ............................................................................................................................................................ 9
2. Packages.................................................................................................................................................................... 11
3. Pin Assignments ....................................................................................................................................................... 12
4. Pin Descriptions ........................................................................................................................................................ 16
5. I/O Circuit Type .......................................................................................................................................................... 65
6. Handling Precautions................................................................................................................................................ 73
6.1 Precautions for Product Design ................................................................................................................................ 73
6.2 Precautions for Package Mounting ........................................................................................................................... 74
6.3 Precautions for Use Environment ............................................................................................................................. 76
7. Handling Devices....................................................................................................................................................... 77
8. Block Diagram ........................................................................................................................................................... 80
9. Memory Size .............................................................................................................................................................. 81
10. Memory Map .............................................................................................................................................................. 81
11. Pin Status In Each CPU State ................................................................................................................................... 87
12. Electrical Characteristics.......................................................................................................................................... 95
12.1 Absolute Maximum Ratings ...................................................................................................................................... 95
12.2 Recommended Operating Conditions....................................................................................................................... 97
12.3 DC Characteristics.................................................................................................................................................. 102
12.3.1 Current Rating ..................................................................................................................................................... 102
12.3.2 Pin Characteristics ............................................................................................................................................... 112
12.4 AC Characteristics .................................................................................................................................................. 114
12.4.1 Main Clock Input Characteristics ......................................................................................................................... 114
12.4.2 Sub Clock Input Characteristics ........................................................................................................................... 115
12.4.3 Built-In CR Oscillation Characteristics ................................................................................................................. 115
12.4.4
12.4.5
Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL).............................. 116
Operating Conditions of USB/Ethernet PLLI2S PLL
(in the Case of Using Main Clock for Input Clock of PLL) .................................................................................... 116
12.4.6 Operating Conditions of Main PLL
(in the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL) .............................................. 117
12.4.7 Reset Input Characteristics.................................................................................................................................. 117
12.4.8 Power-On Reset Timing....................................................................................................................................... 118
12.4.9 GPIO Output Characteristics ............................................................................................................................... 118
12.4.10 External Bus Timing............................................................................................................................................. 119
12.4.11 Base Timer Input Timing...................................................................................................................................... 130
12.4.12 CSIO (SPI) Timing ............................................................................................................................................... 131
12.4.13 External Input Timing ........................................................................................................................................... 164
12.4.14 Quadrature Position/Revolution Counter Timing.................................................................................................. 165
12.4.15 I2C Timing ............................................................................................................................................................ 167
12.4.16 SD Card Interface Timing .................................................................................................................................... 169
12.4.17 ETM/ HTM Timing................................................................................................................................................ 171
12.4.18 JTAG Timing........................................................................................................................................................ 172
12.4.19 Ethernet-MAC Timing .......................................................................................................................................... 173
12.4.20 I2S Timing ............................................................................................................................................................ 178
12.4.21 High-Speed Quad SPI Timing.............................................................................................................................. 183
12.5 12-bit A/D Converter............................................................................................................................................... 185
Document Number: 002-04980 Rev.*A
Page 7 of 207

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