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8S89833 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8S89833
기능 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination
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8S89833 데이터시트, 핀배열, 회로
Low Skew, 1-To-4 Differential-To-LVDS
Fanout Buffer w/Internal Termination
8S89833
Data Sheet
General Description
The 8S89833 is a high speed 1-to-4 Differential-to-LVDS Fanout
Buffer with Internal Termination. The 8S89833 is optimized for high
speed and very low output skew, making it suitable for use in
demanding applications such as SONET, 1 Gigabit and 10 Gigabit
Ethernet, and Fibre Channel. The internally terminated differential
input and VREF_AC pin allow other differential signal families such as
LVPECL, LVDS, and CML to be easily interfaced to the input with
minimal use of external components. The device also has an output
enable pin which may be useful for system test and debug purposes.
The 8S89833 is packaged in a small 3mm x 3mm 16-pin VFQFN
package which makes it ideal for use in space-constrained
applications.
Features
Four differential LVDS outputs
IN, nIN input pair can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: 2GHz
Cycle-to-cycle jitter, RMS: 3.5ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
Output skew: 30ps (maximum)
Part-to-part skew: 200ps (maximum)
Propagation Delay: 600ps (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
IN
50Ω
VT
50Ω
nIN
VREF_AC
EN Pullup
DQ
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
16 15 14 13
Q0 1
12 IN
nQ0 2
11 VT
Q1 3
10 VREF_AC
nQ1 4
9 nIN
5 6 78
8S89833
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B August 24, 2016




8S89833 pdf, 반도체, 판매, 대치품
8S89833 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
Outputs, IO
Continuos Current
Surge Current
Input Current, IN, nIN
4.6V
-0.5V to VDD + 0.5V
10mA
15mA
±50mA
VT Current, IVT
Input Sink/Source, IREF_AC
Operating Temperature Range, TA
Package Thermal Impedance, JA, (Junction-to-Ambient)
Storage Temperature, TSTG
±100mA
± 2mA
-40°C to +85°C
74.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VDD Positive Supply Voltage
IDD Power Supply Current
3.0
Typical
3.3
Maximum
3.6
100
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VIH Input High Voltage
VIL Input Low Voltage
IIH Input High Current
IIL Input Low Current
VDD = VIN = 3.6V
VDD = 3.6V, VIN = 0V
2.2
-0.3
-150
Typical
Maximum
VDD + 0.3
0.8
10
Units
V
V
µA
µA
©2016 Integrated Device Technology, Inc
4
Revision B August 24, 2016

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8S89833 전자부품, 판매, 대치품
8S89833 Data Sheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a Phase
noise plot and is most often the specified plot in many applications.
Phase noise is defined as the ratio of the noise power present in a
1Hz band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency
domain, we get a better understanding of its effects on the desired
application over the entire time record of the signal. It is
mathematically possible to calculate an expected bit error rate given
a phase noise plot.
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 0.03ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "IFR2042 10kHz – 6.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator".
©2016 Integrated Device Technology, Inc
7
Revision B August 24, 2016

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