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8SLVD1212 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8SLVD1212
기능 LVDS Output Fanout Buffer
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8SLVD1212 데이터시트, 핀배열, 회로
1:12, LVDS Output Fanout Buffer
8SLVD1212
Datasheet
General Description
The 8SLVD1212 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVD1212 is
characterized to operate from a 2.5V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
8SLVD1212 ideal for those clock distribution applications demanding
well-defined performance and repeatability. Two selectable
differential inputs and twelve low skew outputs are available. The
integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Twelve low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz (maximum)
• LVCMOS/LVTTL interface levels for the control input select pins
• Output skew: 45ps (max)
• Propagation delay: 310ps (typical)
• Low additive phase jitter, RMS; fREF = 156.25MHz,
10kHz - 20MHz: 77fs (typical)
• Maximum device current consumption (IDD): 213mA
• 2.5V supply voltage
• Lead-free (RoHS 6), 40-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Pin Assignment
SEL
PCLK1
nPCLK1
VREF1
VDD
VDD
VREF0
nPCLK0
PCLK0
nc
40 39 38 37 36 35 34 33 32 31
1
2
3
4
5 8SLVD1212
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
11 12 13 14 15 16 17 18 19 20
GND
nQ7
Q7
nQ6
Q6
nQ5
Q5
nQ4
Q4
GND
40-Lead VFQFN
6.0mm x 6.0mm x 0.9mm package body
©2016 Integrated Device Technology, Inc.
1
Revision 3, July 5, 2016




8SLVD1212 pdf, 반도체, 판매, 대치품
8SLVD1212 Datasheet
Table 1. Pin Descriptions1
Number
Name
Type
Description
34 Q9 Output
35 nQ9 Output
Differential output pair. LVDS interface levels.
36 Q10 Output
37
nQ10
Output
Differential output pair. LVDS interface levels.
38, Q11 Output
39
nQ11
Output
Differential output pair. LVDS interface levels.
40 VDD Power
GND_EP
Power
Power supply pins.
Exposed pad of package. Connect to GND.
NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
k
k
Function Table
Table 3. SEL Input Function Table1
SEL Operation
0 PCLK0, nPCLK0 is the selected differential clock input.
1 PCLK1, nPCLK1 is the selected differential clock input.
Open
Input buffers are disabled and outputs are static.
NOTE 1: SEL is an asynchronous control.
©2016 Integrated Device Technology, Inc.
4
Revision 3, July 5, 2016

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8SLVD1212 전자부품, 판매, 대치품
8SLVD1212 Datasheet
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C1
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fREF
Input
PCLK[0:1],
Frequency nPCLK[0:1]
2 GHz
V/t
Input
PCLK[0:1],
Edge Rate nPCLK[0:1]
1.5 V/ns
tPD
tsk(o)
tsk(p)
tsk(pp)
Propagation Delay2
Output Skew3, 4
PCKx, nPCLKx to any Qx, nQx
for VPP = 0.1V or 0.3V
200 310 500 ps
45 ps
Pulse Skew5, 6
Part-to-Part Skew4, 7
fREF = 100MHz, 500MHz, 1GHz, 1.5GHz
80 ps
300 ps
Buffer Additive Phase
tJIT
Jitter, RMS; refer to
Additive Phase Jitter
fREF = 156.25MHz, VPP = 1.0V, VCMR = 1V
Integration Range: 10kHz – 20MHz
Section
77 90 fs
tR / tF
Output Rise/ Fall Time
20% to 80%
Outputs Loaded with 100
100 200 ps
MUXISOLATION Mux Isolation8
fREF = 100MHz
75 dB
NOTE 1: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Output pulse skew tsk(p) is absolute difference of the propagation delay times: |tPLH - tPHL|.
NOTE 6: Output duty cycle is frequency dependent: odc= input duty cycle +/- ((tsk(p)/2)*(1/output period))*100.
NOTE 7: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.
NOTE 8: Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
©2016 Integrated Device Technology, Inc.
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Revision 3, July 5, 2016

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8SLVD1212

LVDS Output Fanout Buffer

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