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8SLVD1204-33 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8SLVD1204-33
기능 LVDS Output Fanout Buffer
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8SLVD1204-33 데이터시트, 핀배열, 회로
2:4, LVDS Output Fanout Buffer
8SLVD1204-33
DATA SHEET
General Description
The 8SLVD1204-33 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVD1204-33
is characterized to operate from a 3.3V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
8SLVD1204-33 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
Four low skew, low additive jitter LVDS output pairs
Two selectable differential clock input pairs
Differential PCLKx, nPCLKx pairs can accept the following
differential input levels: LVDS, LVPECL
Maximum input clock frequency: 2GHz
LVCMOS/LVTTL interface levels for the control input select pin
Output skew: 20ps (maximum)
Propagation delay: 310ps (maximum)
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
10kHz - 20MHz: 100fs (maximum)
Full 3.3V supply voltage
Lead-free (RoHS 6), 16-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
VDD
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
GND GND
VDD
PCLK1
nPCLK1
Pulldown
Pullup/Pulldown
GND GND
VDD
SEL Pullup/Pulldown
VREF
GND
Reference
Voltage
Generator
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
12 11 10
Q2 13
9
8 VREF
nQ2 14
Q3 15
8SLVD1204-33
8XXXXXX
7 nPCLK0
6 PCLK0
nQ3 16
5 VDD
12 3 4
16-pin, 3mm x 3mm VFQFN Package
8SLVD1204-33 REVSION B 03/11/15
1 ©2015 Integrated Device Technology, Inc.




8SLVD1204-33 pdf, 반도체, 판매, 대치품
8SLVD1204-33 DATA SHEET
Table 4C. Differential Input DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
PCLK0,
IIH
Input High
Current
nPCLK1
PCLK1,
nPCLK1
VDD = VIN = 3.465V
IIL
Input Low
Current
PCLK0,
PCLK1
nPCLK0,
nPCLK1
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-10
-150
VREF
Reference Voltage
for Input Bias
IREF = ±1mA
VDD – 1.50
VPP
VCMR
Peak-to-Peak Voltage;
NOTE 1
Common Mode Input
Voltage; NOTES 1, 2
fREF < 1.5 GHz
fREF 1.5 GHz
0.1
0.2
1.0
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined at the crosspoint.
Typical
VDD – 1.35
Maximum Units
150 µA
µA
µA
VDD – 1.15
1.5
1.5
VDD – 0.6
V
V
V
V
Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
247
1.15
Typical
Maximum
454
50
1.45
50
Units
mV
mV
V
mV
2:4, LVDS OUTPUT FANOUT BUFFER
4
REVSION B 03/11/15

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8SLVD1204-33 전자부품, 판매, 대치품
Parameter Measurement Information
VDD
GND
LVDS Output Load Test Circuit
VDD
nPCLK[0:1]
PCLK[0:1]
GND
Differential Input Level
nPCLK[0:1]
PCLK[0:1]
nQy
Qy
t PLH
tsk(p)= |tPHL - tPLH|
t PHL
Pulse Skew
nQx
Qx
nQy
Qy
Output Skew
8SLVD1204-33 DATA SHEET
Part 1
nQx
Qx
nQy Par t 2
Qy
t sk(pp)
Part-to-Part Skew
nQ[0:3]
Q[0:3]
20%
80%
tR
Output Rise/Fall Time
80%
tF
VOD
20%
REVSION B 03/11/15
7 2:4, LVDS OUTPUT FANOUT BUFFER

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8SLVD1204-33

LVDS Output Fanout Buffer

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