Datasheet.kr   

8SLVP1204 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8SLVP1204
기능 LVPECL Output Fanout Buffer
제조업체 IDT
로고 IDT 로고 



전체 25 페이지

		

No Preview Available !

8SLVP1204 데이터시트, 핀배열, 회로
Low Phase Noise, 2:4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP1204
DATA SHEET
General Description
The 8SLVP1204 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1204 is
characterized to operate from a 3.3V or 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1204 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
Four low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Differential PCLKx pairs can also accept single-ended LVCMOS
levels. See Section, “Applications Information”, section, “Wiring
the Differential Input to Accept Single-Ended Levels” (Figures 1A
and 1B)
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input, (input select)
Output skew: 5ps (typical), at 3.63V
Propagation delay: 200ps (typical), at 3.63V
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz - 20MHz: 40fs (maximum), at 3.63V
Maximum device current consumption (IEE): 60mA (maximum),
at 3.63V
Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply
Lead-free (RoHS 6), 16-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Supports case temperature 105°C operations
Block Diagram
VCC
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
VCC
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
0 fREF
1
SEL Pulldown
VREF
Voltage
Reference
Pin Assignment
16 15 14 13
Q0
VEE 1
12 nQ1
nQ0
SEL 2
11 Q1
Q1
PCLK1 3
10 nQ0
nQ1 nPCLK1 4
9 Q0
5 6 78
Q2
nQ2
Q3
nQ3 8SLVP1204
16-Lead, 3mm x 3mm VFQFN Package
8SLVP1204 REVISION D 6/8/15
1 ©2015 Integrated Device Technology, Inc.




8SLVP1204 pdf, 반도체, 판매, 대치품
8SLVP1204 DATA SHEET
Table 4D. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ±10%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VIH Input High Voltage
VCC = 3.63V
VCC = 2.625V
VIL Input Low Voltage
VCC = 3.63V
VCC = 2.625V
IIH Input High Current SEL VCC = VIN = 3.465V or 2.625V
IIL
Input Low Current SEL
VCC = 3.465V or 2.625V, VIN = 0V
2.2
1.7
-0.3
-0.3
-10
Maximum
VCC + 0.3
VCC + 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
Table 4E. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VIH Input High Voltage
VCC = 3.465V
VCC = 2.625V
VIL Input Low Voltage
VCC = 3.465V
VCC = 2.625V
IIH Input High Current SEL VCC = VIN = 3.465V or 2.625V
IIL
Input Low Current SEL
VCC = 3.465V or 2.625V, VIN = 0V
2.2
1.7
-0.3
-0.3
-10
VCC + 0.3
VCC + 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
4
REVISION D 6/8/15

4페이지










8SLVP1204 전자부품, 판매, 대치품
8SLVP1204 DATA SHEET
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications
after thermal equilibrium has been reached under these conditions.
NOTE 2. Measured from the differential input crossing point to the differential output crosspoint.
NOTE 3. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
point.
NOTE 4. This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross
point.
NOTE 6. Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
NOTE 7. For single-ended LVCMOS input applications, refer to the Applications section Wiring the Differential Input Levels to Accept Sin-
gle-ended Levels (Figures 1 and 2).
NOTE 8. VIL should not be less than -0.3V. VIH should not be higher than VCC.
NOTE 9. Common mode input voltage is defined as the crosspoint.
Table 5B. AC Electrical Characteristics, VCC = 3.3V ±10%, VEE = 0V, TA = -40°C to 85°C1
Symbol
Parameter
Test Conditions
Minimum
fREF
Input
PCLK[0:1],
Frequency nPCLK[0:1]
Typical
Maximum Units
2 GHz
V/t
Input
PCLK[0:1],
Edge Rate nPCLK[0:1]
1.5 V/ns
tPD
tsk(o)
tsk(i)
tsk(p)
tsk(pp)
Propagation Delay2
Output Skew3 4
Input Skew4
Pulse Skew
Part-to-Part Skew4 5
PCKx, nPCLKx to any Qx, nQx
for VPP = 0.1V or 0.3V
fREF = 100MHz
120 230 325 ps
6 30 ps
6 55 ps
7 25 ps
200 ps
tR / tF
MUXISOLATION
VPP
Output Rise/ Fall Time
Mux Isolation6
Peak-to-Peak Input
Voltage7
VCMR
Common Mode Input
Voltage7 8 9
VO(pp)
VDIFF_OUT
Output Voltage Swing,
Peak-to-Peak
Differential Output
Voltage Swing,
Peak-to-Peak
20% to 80%
fREF = 100MHz
fREF < 1.5 GHz
fREF > 1.5 GHz
VPP = > 247mV
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
35
0.1
0.2
1.0
0.8
0.45
0.4
0.9
0.8
77
0.75
0.65
1.5
1.3
200
1.5
1.5
VCC – 0.6
VCC – 0.6
1.0
1.0
2.0
2.0
ps
dB
V
V
V
V
V
V
V
V
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications
after thermal equilibrium has been reached under these conditions.
NOTE 2. Measured from the differential input crossing point to the differential output crosspoint.
NOTE 3. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
point.
NOTE 4. This parameter is defined in accordance with JEDEC Standard 65
NOTE 5. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cros-
spoint.
REVISION D 6/8/15
7 LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER

7페이지



구       성총 25 페이지
다운로드[ 8SLVP1204.PDF 데이터시트 ]
구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

휴대전화 : 010-3582-2743


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877, [ 홈페이지 ]



링크공유

링크 :

관련 데이터시트

부품번호상세설명 및 기능제조사
8SLVP1204

LVPECL Output Fanout Buffer

IDT
IDT
8SLVP1208

LVPECL Output Fanout Buffer

IDT
IDT

DataSheet.kr    |   2019   |  연락처   |  링크모음   |   검색  |   사이트맵