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8SLVP1208 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8SLVP1208
기능 LVPECL Output Fanout Buffer
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8SLVP1208 데이터시트, 핀배열, 회로
Low Phase Noise, 1-to-8, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP1208
DATA SHEET
General Description
The 8SLVP1208 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1208 is
characterized to operate from a 3.3V and 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1208 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and eight low skew outputs are available.
The integrated bias voltage generators enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
Eight low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input (input select)
Output skew: 28ps (typical)
Propagation delay: 410ps (maximum)
Low additive phase jitter, RMS: 54.1fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (IEE): 141mA
Available in lead-free (RoHS 6), 28-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input to Accept Single-Ended Levels
(Figure 1A and Figure 1B)
Block Diagram
VCC
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
VCC
PCLK1
nPCLK1
Pulldown
Pullup/Pulldown
0 fREF
1
SEL Pulldown
VREF
Voltage
Reference
8SLVP1208 REVISION 1 08/28/14
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6 8SLVP1208
nQ6 28-Lead LFCSP
Q7 5mm x 5mm x 0.75mm package body
nQ7 NB Package
Top View
1 ©2014 Integrated Device Technology, Inc.




8SLVP1208 pdf, 반도체, 판매, 대치품
8SLVP1208 DATA SHEET
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
VIH Input High Voltage
VCC = 3.465V
VCC = 2.625V
2.2
1.7
VIL Input Low Voltage
VCC = 3.465V
VCC = 2.625V
-0.3
-0.3
IIH
Input High
Current
SEL
VCC = VIN = 3.465V or 2.625V
VCC + 0.3
VCC + 0.3
0.8
0.7
150
IIL
Input Low
Current
SEL VCC = 3.465V or 2.625V, VIN = 0V
-10
Units
V
V
V
V
µA
µA
Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C1
Symbol
Parameter
Test Conditions
Minimum
Typical
Input High PCLK0, nPCLK0
IIH
Current
PCLK1, nPCLK1
VCC = VIN = 3.465V
IIL
Input Low PCLK0, PCLK1
Current
nPCLK0, nPCLK1
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
VREF
Reference Voltage for Input
Bias
IREF = 2mA
VOH Output High Voltage2
VOL Output Low Voltage2
NOTE 1: Input and output parameters vary 1:1 with VCC.
NOTE 2: Outputs terminated with 50to VCC – 2V.
-10
-150
VCC – 1.83
VCC – 1.23
VCC – 1.97
VCC – 1.54
VCC – 1.16
VCC – 1.90
Maximum Units
150 µA
µA
µA
VCC – 1.25
VCC – 0.80
VCC – 1.70
V
V
V
Table 4E. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C1
Symbol
Parameter
Test Conditions
Minimum Typical
Input High PCLK0, nPCLK0
IIH
Current
PCLK1, nPCLK1 VCC = VIN = 2.625V
IIL
Input Low
Current
PCLK0, PCLK1 VCC = 2.625V, VIN = 0V
nPCLK0, nPCLK1 VCC = 2.625V, VIN = 0V
VREF
Reference Voltage for Input
Bias
IREF = 2mA
VOH Output High Voltage2
VOL Output Low Voltage2
NOTE 1: Input and output parameters vary 1:1 with VCC.
NOTE 2: Outputs terminated with 50to VCC – 2V.
-10
-150
VCC – 1.64
VCC – 1.21
VCC – 1.92
VCC – 1.36
VCC – 1.00
VCC – 1.80
Maximum
150
VCC – 1.09
VCC – 0.79
VCC – 1.67
Units
µA
µA
µA
V
V
V
LOW PHASE NOISE, 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
4
REVISION 1 08/28/14

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8SLVP1208 전자부품, 판매, 대치품
8SLVP1208 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHz, VPP = 1V
12kHz to 20MHz = 35.9fs (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
REVISION 1 08/28/14
7 LOW PHASE NOISE, 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER

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