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8SLVP2104 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8SLVP2104
기능 LVPECL Output Fanout Buffer
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8SLVP2104 데이터시트, 핀배열, 회로
Low Phase Noise, Dual 1-to-4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP2104
DATA SHEET
General Description
The 8SLVP2104I is a high-performance differential dual LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVP2104I is characterized to operate from a 3.3V or 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8SLVP2104I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and four low skew
outputs are available. The integrated bias voltage reference enable
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
Two 1:4, low skew, low additive jitter LVPECL output pairs
Two differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
Output skew: 8ps (typical)
Propagation delay: 270ps (maximum)
Low additive phase jitter, RMS: 47fs (maximum)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (IEE): 93mA (maximum)
Available in lead-free (RoHS 6), 28-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Supports case temperature 105°C operations
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).
Block Diagram
PCLKA
nPCLKA
VCC
VREFA
Voltage
Reference
PCLKB
nPCLKB
VCC
VREFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
Pin Assignment
21 20 19 18 17 16 15
QB0 22
14 VEE
nQB0 23
13 nQA0
QB1 24
12 QA0
nQB1 25
11 VREFA
QB2 26
10 nPCLKA
nQB2 27
9 PCLKA
VCC 28
8 VCC
1 23 45 67
8SLVP2104I
28-Lead VFQFN
5mm x 5mm x 0.75mm package body
NB Package
Top View
8SLVP2104 REVISION C 6/8/15
1 ©2015 Integrated Device Technology, Inc.




8SLVP2104 pdf, 반도체, 판매, 대치품
8SLVP2104 DATA SHEET
Table 3C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
IIH
Input
High
Current
PCLKA, nPCLKA;
PCLKB, nPCLKB
VCC = VIN = 3.465V
Input
PCLKA, PCLKB
VCC = 3.465V, VIN = 0V
-10
IIL Low
Current
nPCLKA, nPCLKB
VCC = 3.465V, VIN = 0V
-150
VREFA,
VREFB
VOH
VOL
Reference Voltage for Input Bias
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IREF = 2mA
VCC – 1.6
VCC – 1.1
VCC – 2.0
NOTE: Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50to VCC – 2V.
Typical
VCC – 1.3
VCC – 0.9
VCC – 1.5
Table 3D. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
IIH
Input
High
Current
PCLKA, nPCLKA;
PCLKB, nPCLKB
VCC = VIN = 2.625V
Input
PCLKA, PCLKB
VCC = 2.625V, VIN = 0V
-10
IIL Low
Current
nPCLKA, nPCLKB
VCC = 2.625V, VIN = 0V
-150
VREFA,
VREFB
VOH
VOL
Reference Voltage for Input Bias
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IREF = 2mA
VCC – 1.6
VCC – 1.1
VCC – 2.0
NOTE: Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50to VCC – 2V.
Typical
VCC – 1.3
VCC – 0.9
VCC – 1.5
Maximum Units
150 µA
VCC – 1.1
VCC – 0.8
VCC – 1.4
µA
µA
V
V
V
Maximum Units
150 µA
VCC – 1.1
VCC – 0.8
VCC – 1.4
µA
µA
V
V
V
LOW PHASE NOISE, DUAL 1-TO-4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
4
REVISION C 6/8/15

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8SLVP2104 전자부품, 판매, 대치품
8SLVP2104 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
REVISION C 6/8/15
7 LOW PHASE NOISE, DUAL 1-TO-4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER

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