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8SLVP2106 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8SLVP2106
기능 LVPECL Output Fanout Buffer
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8SLVP2106 데이터시트, 핀배열, 회로
Low Phase Noise, Dual 1-to-6, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP2106
DATA SHEET
General Description
The 8SLVP2106 is a high-performance differential dual 1:6 LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVP2106 is characterized to operate from a 3.3V or 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8SLVP2106 ideal for those clock distribution
applications demanding well-defined performance and repeatability.
Two independent buffers with six low skew outputs each are
available. The integrated bias voltage references enable easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Block Diagram
PCLKA
nPCLKA
VCC
VREFA
Voltage
Reference
PCLKB
nPCLKB
VCC
VREFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
QA5
nQA5
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
QB5
nQB5
Features
Two 1:6, low skew, low additive jitter LVPECL fanout buffers
Two differential clock inputs
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL, CML
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (typical)
Propagation delay: 340ps (maximum)
Low additive phase jitter, RMS: 54fs (maximum)
fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: VCC = 3.3V)
Full 3.3V and 2.5V supply voltage modes
Maximum device current consumption (IEE): 114mA
Available in Lead-free (RoHS 6), 40-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Supports case temperature 105°C operations
Pin Assignment
30 29 28 27 26 25 24 23 22 21
VCC 31
QB2 32
nQB2 33
QB3 34
nQB3 35
QB4 36
nQB4 37
QB5 38
nQB5 39
VCC 40
8SLVP2106i
40-lead VFQFN
6mm x 6mm x 0.925mm package body
NL Package
Top View
1 2 3 4 5 6 7 8 9 10
20 VCC
19 nQA3
18 QA3
17 nQA2
16 QA2
15 nQA1
14 QA1
13 nQA0
12 QA0
11 VCC
8SLVP2106 REVISION B 6/9/15
1 ©2015 Integrated Device Technology, Inc.




8SLVP2106 pdf, 반도체, 판매, 대치품
8SLVP2106 DATA SHEET
Table 3C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
IIH
Input High PCLKA, nPCLKA
Current PCLKB, nPCLKB
VCC = VIN = 3.465V
150 µA
IIL
VREFx
Input Low PCLKA, PCLKB
Current nPCLKA, nPCLKB
Reference Voltage for Input
Bias
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
IREF = 2mA
-10
-150
VCC – 1.82 VCC – 1.48 VCC – 1.27
µA
µA
V
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VCC – 1.05 VCC – 0.89 VCC – 0.72
VCC – 1.50 VCC – 1.38 VCC – 1.26
V
V
NOTE: VREFx denotes VREFA and VREFB.
NOTE 1: Outputs terminated with 50to VCC – 2V.
Table 3D. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
IIH
Input High Current
PCLKA, nPCLKA
PCLKB, nPCLKB
VCC = VIN = 2.625V
150 µA
IIL
VREFx
PCLKA, PCLKB
Input Low Current
nPCLKA, nPCLKB
Reference Voltage for Input Bias;
NOTE 2
VCC = 2.625V, VIN = 0V
VCC = 2.625V, VIN = 0V
IREF = 2mA
-10
-150
VCC – 1.81 VCC – 1.47 VCC – 1.27
µA
µA
V
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VCC – 1.05 VCC – 0.89 VCC – 0.73
VCC – 1.48 VCC – 1.36 VCC – 1.23
V
V
NOTE: VREFx denotes VREFA and VREFB.
NOTE 1: Outputs terminated with 50to VCC – 2V.
NOTE 2: For VCC < 3V, the use of an alternate bias voltage source is recommended.
LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
4
REVISION B 6/9/15

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8SLVP2106 전자부품, 판매, 대치품
8SLVP2106 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHZ, VPP = 1V
12kHz to 20MHz = 46fs (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
REVISION B 6/9/15
7 LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER

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