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8SLVD2102 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8SLVD2102
기능 LVDS Output Fanout Buffer
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8SLVD2102 데이터시트, 핀배열, 회로
Dual 1:2, LVDS Output Fanout Buffer
8SLVD2102
DATA SHEET
General Description
The 8SLVD2102 is a high-performance differential dual 1:2 LVDS
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVD2102 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVD2102 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
independent buffers with two low skew outputs each are available.
The integrated bias voltage generators enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
Two 1:2, low skew, low additive jitter LVDS fanout buffers
Two differential clock inputs
Differential pairs can accept the following differential input
levels: LVDS and LVPECL
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (maximum)
Propagation delay: 300ps (maximum)
Low additive phase jitter: 200fs, RMS (maximum);
fREF = 156.25MHz, VPP = 1V, VCMR = 1V,
Integration Range 10kHz - 20MHz
2.5V supply voltage
Maximum device current consumption (IDD): 90mA
Lead-free (RoHS 6) 16-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Block Diagram
VDD
PCLKA
nPCLKA
PCLKB
nPCLKB
VDD
VREF
EN
Voltage
VDD Reference
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
Pin Assignment
16 15 14 13
GND 1
12 nQA1
EN 2
PCLKB 3
8SLVD2102I
8XXXXXX
11 QA1
10 nQA0
nPCLKB 4
9 QA0
56 7 8
16-pin, 3.0mm x 3.0mm VFQFN Package
8SLVD2102 REVISION 2 11/11/15 1 ©2015 Integrated Device Technology, Inc.




8SLVD2102 pdf, 반도체, 판매, 대치품
8SLVD2102 DATA SHEET
Table 4C. Differential Input Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
IIH
Input
PCLKA, nPCLKA
High Current PCLKB, nPCLKB
VDD = VIN = 2.625V
IIL
Input
PCLKA, PCLKB
Low Current nPCLKA, nPCLKB
VREF_AC Reference Voltage for Input Bias
VPP Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage;
NOTE 1, 2
VDD = 2.625V, VIN = 0V
VDD = 2.625V, VIN = 0V
VDD = 2.5V, IREF = +100µA
fREF < 1.5 GHz
fREF > 1.5 GHz
-10
-150
1.00
0.15
0.2
1
NOTE 1: VIL should not be less than -0.3V. VIH should be less than VDD.
NOTE 2: Common mode input voltage is defined at the crosspoint.
Table 4D. LVDS Output DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C°
Symbol Parameter
Test Conditions
Minimum
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
100termination between nQx, Qx
100termination between nQx, Qx
100termination between nQx, Qx
100termination between nQx, Qx
247
1.0
Typical
Maximum Units
150 µA
µA
µA
1.35 V
1.6 V
1.6 V
VDD – VPP/2
V
Typical
Maximum
454
50
1.4
50
Units
mV
mV
V
mV
DUAL 1:2, LVDS OUTPUT FANOUT BUFFER
4
REVISION 2 11/11/15

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8SLVD2102 전자부품, 판매, 대치품
Parameter Measurement Information
VDD
LVDS Output Load Test Circuit
nPCLKA[0:1],
nPCLKB[0:1]
PCLKA[0:1],
PCLKB[0:1]
nQy
Qy
t PLH
tsk(p)= |tPHL - tPLH|
t PHL
Pulse Skew
VDD
nPCLKA[0:1],
nPCLKB[0:1]
PCLKA[0:1],
PCLKB[0:1]
GND
Differential Input Level
nQx
Qx
nQy
Qy
Output Skew
Part 1
nQx
Qx
nQy Par t 2
Qy
t sk(pp)
Part-to-Part Skew
nQA[0:1],
nQB[0:1]
QA[0:1], 20%
nQB[0:1]
80%
tR
Output Rise/Fall Time
8SLVD2102 DATA SHEET
80%
tF
VOD
20%
REVISION 2 11/11/15
7 DUAL 1:2, LVDS OUTPUT FANOUT BUFFER

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